CLKMGR Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.540s 282.416us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.080s 118.387us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 13.130s 4.010ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.670s 100.170us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.800s 37.154us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
clkmgr_csr_aliasing 1.670s 100.170us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.160s 180.971us 50 50 100.00
V2 trans_enables clkmgr_trans 1.920s 422.052us 50 50 100.00
V2 extclk clkmgr_extclk 1.340s 230.192us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.960s 133.101us 50 50 100.00
V2 jitter clkmgr_smoke 1.540s 282.416us 50 50 100.00
V2 frequency clkmgr_frequency 17.390s 2.356ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.150s 2.181ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.390s 2.356ms 50 50 100.00
V2 stress_all clkmgr_stress_all 57.710s 8.230ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.950s 156.206us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.150s 173.042us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.890s 1.311ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.890s 1.311ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.080s 118.387us 5 5 100.00
clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
clkmgr_csr_aliasing 1.670s 100.170us 5 5 100.00
clkmgr_same_csr_outstanding 2.280s 490.624us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.080s 118.387us 5 5 100.00
clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
clkmgr_csr_aliasing 1.670s 100.170us 5 5 100.00
clkmgr_same_csr_outstanding 2.280s 490.624us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.250s 1.079ms 5 5 100.00
clkmgr_tl_intg_err 4.040s 637.067us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.040s 546.649us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.040s 546.649us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.040s 546.649us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.040s 546.649us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.840s 542.958us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.040s 637.067us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.390s 2.356ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.150s 2.181ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.040s 546.649us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.580s 292.726us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.340s 225.488us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 2.030s 446.746us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.400s 227.252us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.330s 177.365us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.250s 1.079ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.080s 133.321us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.250s 1.079ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.000s 1.248ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 35.935m 643.386ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results