CLKMGR Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.410s	242.343us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.950s	70.332us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.130s	1.467ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.760s	709.814us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.630s	378.019us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
		clkmgr_csr_aliasing	2.760s	709.814us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.920s	57.859us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.170s	461.620us	50	50	100.00
V2	extclk	clkmgr_extclk	1.190s	155.738us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.150s	209.265us	50	50	100.00
V2	jitter	clkmgr_smoke	1.410s	242.343us	50	50	100.00
V2	frequency	clkmgr_frequency	18.250s	2.357ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.620s	2.298ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.250s	2.357ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.463m	12.270ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.790s	38.719us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.190s	174.917us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.050s	417.143us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.050s	417.143us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.950s	70.332us	5	5	100.00
		clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
		clkmgr_csr_aliasing	2.760s	709.814us	5	5	100.00
		clkmgr_same_csr_outstanding	1.580s	63.665us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.950s	70.332us	5	5	100.00
		clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
		clkmgr_csr_aliasing	2.760s	709.814us	5	5	100.00
		clkmgr_same_csr_outstanding	1.580s	63.665us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.130s	1.438ms	5	5	100.00
		clkmgr_tl_intg_err	3.740s	490.393us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.340s	305.849us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.340s	305.849us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.340s	305.849us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.340s	305.849us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.230s	790.922us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.740s	490.393us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.250s	2.357ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.620s	2.298ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.340s	305.849us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.610s	342.896us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.550s	282.205us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.540s	252.409us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.390s	198.679us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.720s	346.374us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.130s	1.438ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.070s	118.231us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.130s	1.438ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.060s	1.323ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	31.871m	494.627ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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