CLKMGR Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.680s 310.556us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.810s 31.083us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.780s 1.335ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.370s 303.215us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.320s 134.284us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
clkmgr_csr_aliasing 2.370s 303.215us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.130s 120.565us 50 50 100.00
V2 trans_enables clkmgr_trans 1.450s 192.104us 50 50 100.00
V2 extclk clkmgr_extclk 1.320s 217.336us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.180s 189.195us 50 50 100.00
V2 jitter clkmgr_smoke 1.680s 310.556us 50 50 100.00
V2 frequency clkmgr_frequency 19.120s 2.356ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.720s 2.422ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.120s 2.356ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.454m 11.570ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.990s 113.243us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.080s 115.970us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.250s 709.604us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.250s 709.604us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.810s 31.083us 5 5 100.00
clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
clkmgr_csr_aliasing 2.370s 303.215us 5 5 100.00
clkmgr_same_csr_outstanding 2.720s 600.889us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.810s 31.083us 5 5 100.00
clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
clkmgr_csr_aliasing 2.370s 303.215us 5 5 100.00
clkmgr_same_csr_outstanding 2.720s 600.889us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.690s 610.501us 5 5 100.00
clkmgr_tl_intg_err 3.490s 386.965us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.180s 125.100us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.180s 125.100us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.180s 125.100us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.180s 125.100us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.130s 544.929us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.490s 386.965us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.120s 2.356ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.720s 2.422ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.180s 125.100us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.910s 377.367us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.610s 260.940us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.190s 144.071us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.750s 330.796us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.320s 188.420us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.690s 610.501us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.020s 113.448us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.690s 610.501us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.900s 1.092ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 25.721m 441.971ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results