CLKMGR Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.520s	267.983us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.100s	121.229us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.100s	428.716us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.830s	104.241us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.200s	445.926us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
		clkmgr_csr_aliasing	1.830s	104.241us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.060s	118.884us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.520s	243.754us	50	50	100.00
V2	extclk	clkmgr_extclk	1.590s	267.955us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.930s	119.557us	50	50	100.00
V2	jitter	clkmgr_smoke	1.520s	267.983us	50	50	100.00
V2	frequency	clkmgr_frequency	19.480s	2.476ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.040s	2.302ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.480s	2.476ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.307m	10.878ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.770s	39.957us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.950s	359.618us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.410s	251.744us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.410s	251.744us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.100s	121.229us	5	5	100.00
		clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
		clkmgr_csr_aliasing	1.830s	104.241us	5	5	100.00
		clkmgr_same_csr_outstanding	1.740s	280.707us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.100s	121.229us	5	5	100.00
		clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
		clkmgr_csr_aliasing	1.830s	104.241us	5	5	100.00
		clkmgr_same_csr_outstanding	1.740s	280.707us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.260s	313.769us	5	5	100.00
		clkmgr_tl_intg_err	3.280s	327.937us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.660s	688.445us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.660s	688.445us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.660s	688.445us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.660s	688.445us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.220s	530.271us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.280s	327.937us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.480s	2.476ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.040s	2.302ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.660s	688.445us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.290s	487.459us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.770s	339.922us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.320s	166.617us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.300s	212.155us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	2.100s	448.688us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.260s	313.769us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.060s	141.033us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.260s	313.769us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.040s	1.271ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	31.381m	473.387ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.76	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:753) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 26.clkmgr_stress_all_with_rand_reset.25792050203584307486883584745761654461425297252765512939798922906668810322736
      Line 748, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20050258980 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 20050258980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.05.22_04.46.31
• 2024.05.20_04.19.33
• 2024.05.17_06.48.43
• 2024.05.15_03.15.44
• 2024.05.13_04.05.23