CLKMGR Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.630s 276.632us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.970s 68.813us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.110s 1.091ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.260s 326.142us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.820s 202.584us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
clkmgr_csr_aliasing 2.260s 326.142us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.100s 118.679us 50 50 100.00
V2 trans_enables clkmgr_trans 1.800s 323.607us 50 50 100.00
V2 extclk clkmgr_extclk 1.510s 259.750us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.110s 154.753us 50 50 100.00
V2 jitter clkmgr_smoke 1.630s 276.632us 50 50 100.00
V2 frequency clkmgr_frequency 18.260s 2.357ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.230s 2.415ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.260s 2.357ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.232m 10.148ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.030s 161.355us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.290s 179.259us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.190s 180.177us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.190s 180.177us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.970s 68.813us 5 5 100.00
clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
clkmgr_csr_aliasing 2.260s 326.142us 5 5 100.00
clkmgr_same_csr_outstanding 1.870s 244.772us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.970s 68.813us 5 5 100.00
clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
clkmgr_csr_aliasing 2.260s 326.142us 5 5 100.00
clkmgr_same_csr_outstanding 1.870s 244.772us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.360s 307.768us 5 5 100.00
clkmgr_tl_intg_err 3.300s 337.480us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.920s 521.685us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.920s 521.685us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.920s 521.685us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.920s 521.685us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.570s 353.407us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.300s 337.480us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.260s 2.357ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.230s 2.415ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.920s 521.685us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.340s 507.715us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.300s 180.157us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.680s 300.448us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.600s 273.225us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.300s 195.896us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.360s 307.768us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.260s 189.115us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.360s 307.768us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.490s 1.267ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 40.211m 658.914ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.11 95.68 100.00 100.00 98.71 97.02 98.80

Past Results