CLKMGR Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.770s 320.328us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.940s 19.794us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 12.200s 2.225ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.950s 581.288us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.960s 73.654us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
clkmgr_csr_aliasing 2.950s 581.288us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.010s 94.002us 50 50 100.00
V2 trans_enables clkmgr_trans 2.250s 445.287us 50 50 100.00
V2 extclk clkmgr_extclk 1.330s 189.697us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.890s 96.031us 50 50 100.00
V2 jitter clkmgr_smoke 1.770s 320.328us 50 50 100.00
V2 frequency clkmgr_frequency 17.710s 2.119ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.770s 2.421ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.710s 2.119ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.166m 9.797ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.020s 164.973us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.180s 156.152us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.650s 333.249us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.650s 333.249us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.940s 19.794us 5 5 100.00
clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
clkmgr_csr_aliasing 2.950s 581.288us 5 5 100.00
clkmgr_same_csr_outstanding 2.300s 384.555us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.940s 19.794us 5 5 100.00
clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
clkmgr_csr_aliasing 2.950s 581.288us 5 5 100.00
clkmgr_same_csr_outstanding 2.300s 384.555us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.030s 1.046ms 5 5 100.00
clkmgr_tl_intg_err 3.350s 392.079us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.270s 1.004ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.270s 1.004ms 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.270s 1.004ms 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.270s 1.004ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.270s 178.164us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.350s 392.079us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.710s 2.119ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.770s 2.421ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.270s 1.004ms 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.960s 384.759us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.320s 147.779us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.600s 288.307us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.590s 267.300us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.700s 302.062us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.030s 1.046ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.120s 131.743us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.030s 1.046ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.590s 1.259ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 34.554m 449.799ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results