CLKMGR Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.330s 164.617us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.900s 39.198us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.740s 1.861ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.130s 149.105us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.990s 37.783us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
clkmgr_csr_aliasing 2.130s 149.105us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.120s 130.804us 50 50 100.00
V2 trans_enables clkmgr_trans 1.370s 146.676us 50 50 100.00
V2 extclk clkmgr_extclk 1.680s 271.128us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.100s 142.340us 50 50 100.00
V2 jitter clkmgr_smoke 1.330s 164.617us 50 50 100.00
V2 frequency clkmgr_frequency 17.050s 2.239ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.040s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.050s 2.239ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.368m 11.448ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.810s 95.941us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.410s 253.725us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.970s 632.058us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.970s 632.058us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.900s 39.198us 5 5 100.00
clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
clkmgr_csr_aliasing 2.130s 149.105us 5 5 100.00
clkmgr_same_csr_outstanding 1.740s 211.544us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.900s 39.198us 5 5 100.00
clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
clkmgr_csr_aliasing 2.130s 149.105us 5 5 100.00
clkmgr_same_csr_outstanding 1.740s 211.544us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.740s 1.402ms 5 5 100.00
clkmgr_tl_intg_err 3.810s 479.622us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.630s 1.291ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.630s 1.291ms 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.630s 1.291ms 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.630s 1.291ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.820s 1.192ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.810s 479.622us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.050s 2.239ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.040s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.630s 1.291ms 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.350s 137.927us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.900s 354.218us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.400s 247.880us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.570s 281.281us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.250s 146.671us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.740s 1.402ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.970s 61.179us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.740s 1.402ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 8.010s 2.594ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 27.756m 295.087ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results