CLKMGR Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.170s 136.649us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.070s 127.009us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.650s 400.634us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.790s 94.858us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.720s 102.416us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
clkmgr_csr_aliasing 1.790s 94.858us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.930s 67.831us 50 50 100.00
V2 trans_enables clkmgr_trans 1.950s 369.605us 50 50 100.00
V2 extclk clkmgr_extclk 1.560s 245.107us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.880s 95.837us 50 50 100.00
V2 jitter clkmgr_smoke 1.170s 136.649us 50 50 100.00
V2 frequency clkmgr_frequency 16.740s 2.362ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.680s 2.175ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 16.740s 2.362ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.151m 9.505ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.870s 88.383us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.200s 144.324us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.250s 1.520ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.250s 1.520ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.070s 127.009us 5 5 100.00
clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
clkmgr_csr_aliasing 1.790s 94.858us 5 5 100.00
clkmgr_same_csr_outstanding 3.130s 771.742us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.070s 127.009us 5 5 100.00
clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
clkmgr_csr_aliasing 1.790s 94.858us 5 5 100.00
clkmgr_same_csr_outstanding 3.130s 771.742us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.370s 1.084ms 5 5 100.00
clkmgr_tl_intg_err 3.820s 544.477us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.670s 465.147us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.670s 465.147us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.670s 465.147us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.670s 465.147us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.990s 697.081us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.820s 544.477us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 16.740s 2.362ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.680s 2.175ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.670s 465.147us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.410s 520.970us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.630s 294.171us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.410s 185.569us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.590s 275.540us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.300s 174.476us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.370s 1.084ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.940s 60.799us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.370s 1.084ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.440s 1.290ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 18.971m 187.614ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results