CLKMGR Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.370s 212.956us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.870s 43.814us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.690s 785.225us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.510s 293.033us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.580s 322.617us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
clkmgr_csr_aliasing 2.510s 293.033us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.010s 85.364us 50 50 100.00
V2 trans_enables clkmgr_trans 1.870s 324.847us 50 50 100.00
V2 extclk clkmgr_extclk 1.330s 187.524us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.900s 94.080us 50 50 100.00
V2 jitter clkmgr_smoke 1.370s 212.956us 50 50 100.00
V2 frequency clkmgr_frequency 17.870s 2.363ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.640s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.870s 2.363ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.502m 14.258ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.850s 72.958us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.570s 297.267us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.470s 740.569us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.470s 740.569us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.870s 43.814us 5 5 100.00
clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
clkmgr_csr_aliasing 2.510s 293.033us 5 5 100.00
clkmgr_same_csr_outstanding 1.670s 80.456us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.870s 43.814us 5 5 100.00
clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
clkmgr_csr_aliasing 2.510s 293.033us 5 5 100.00
clkmgr_same_csr_outstanding 1.670s 80.456us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.290s 337.077us 5 5 100.00
clkmgr_tl_intg_err 4.830s 882.012us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.480s 541.024us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.480s 541.024us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.480s 541.024us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.480s 541.024us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.140s 970.363us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.830s 882.012us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.870s 2.363ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.640s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.480s 541.024us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.720s 299.902us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.720s 297.697us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.320s 227.653us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.830s 378.733us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.760s 342.045us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.290s 337.077us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.330s 223.826us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.290s 337.077us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 8.940s 2.783ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 22.071m 308.193ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results