CLKMGR Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.410s 206.395us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.140s 150.743us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.600s 748.174us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.660s 90.466us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.370s 462.421us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
clkmgr_csr_aliasing 1.660s 90.466us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.980s 83.566us 50 50 100.00
V2 trans_enables clkmgr_trans 1.750s 281.547us 50 50 100.00
V2 extclk clkmgr_extclk 1.160s 88.185us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.970s 75.057us 50 50 100.00
V2 jitter clkmgr_smoke 1.410s 206.395us 50 50 100.00
V2 frequency clkmgr_frequency 18.200s 2.476ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 14.770s 1.942ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.200s 2.476ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.385m 15.504ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.790s 61.966us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.240s 135.604us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.130s 647.379us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.130s 647.379us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.140s 150.743us 5 5 100.00
clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
clkmgr_csr_aliasing 1.660s 90.466us 5 5 100.00
clkmgr_same_csr_outstanding 1.690s 167.559us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.140s 150.743us 5 5 100.00
clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
clkmgr_csr_aliasing 1.660s 90.466us 5 5 100.00
clkmgr_same_csr_outstanding 1.690s 167.559us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.630s 482.209us 5 5 100.00
clkmgr_tl_intg_err 4.110s 684.216us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.310s 460.645us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.310s 460.645us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.310s 460.645us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.310s 460.645us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.980s 935.281us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.110s 684.216us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.200s 2.476ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 14.770s 1.942ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.310s 460.645us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.500s 510.707us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 2.010s 419.992us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.190s 146.588us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.030s 409.411us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.370s 193.743us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.630s 482.209us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.180s 144.196us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.630s 482.209us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.780s 2.513ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 55.531m 845.015ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results