CLKMGR Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.190s 146.491us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.910s 68.992us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 6.300s 275.112us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.920s 115.110us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.060s 165.412us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
clkmgr_csr_aliasing 1.920s 115.110us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.310s 224.483us 50 50 100.00
V2 trans_enables clkmgr_trans 2.110s 412.332us 50 50 100.00
V2 extclk clkmgr_extclk 1.280s 186.299us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.950s 111.966us 50 50 100.00
V2 jitter clkmgr_smoke 1.190s 146.491us 50 50 100.00
V2 frequency clkmgr_frequency 19.310s 2.481ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.550s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.310s 2.481ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.574m 12.583ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.810s 80.081us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.970s 77.209us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.360s 494.088us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.360s 494.088us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.910s 68.992us 5 5 100.00
clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
clkmgr_csr_aliasing 1.920s 115.110us 5 5 100.00
clkmgr_same_csr_outstanding 1.860s 283.607us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.910s 68.992us 5 5 100.00
clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
clkmgr_csr_aliasing 1.920s 115.110us 5 5 100.00
clkmgr_same_csr_outstanding 1.860s 283.607us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.650s 1.161ms 5 5 100.00
clkmgr_tl_intg_err 3.950s 706.279us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.600s 339.944us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.600s 339.944us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.600s 339.944us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.600s 339.944us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.860s 1.483ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.950s 706.279us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.310s 2.481ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.550s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.600s 339.944us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.580s 281.369us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.460s 243.486us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.500s 229.786us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.440s 202.244us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.370s 171.779us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.650s 1.161ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.940s 63.869us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.650s 1.161ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.660s 1.378ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 29.312m 446.792ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results