CLKMGR Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.380s 195.960us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.900s 43.399us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.980s 1.629ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.760s 136.691us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.050s 118.309us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
clkmgr_csr_aliasing 1.760s 136.691us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.050s 102.005us 50 50 100.00
V2 trans_enables clkmgr_trans 1.910s 387.385us 50 50 100.00
V2 extclk clkmgr_extclk 1.780s 313.494us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.930s 95.398us 50 50 100.00
V2 jitter clkmgr_smoke 1.380s 195.960us 50 50 100.00
V2 frequency clkmgr_frequency 19.060s 2.360ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.460s 2.422ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.060s 2.360ms 50 50 100.00
V2 stress_all clkmgr_stress_all 2.284m 18.401ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 99.759us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.250s 167.837us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 8.170s 2.192ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 8.170s 2.192ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.900s 43.399us 5 5 100.00
clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
clkmgr_csr_aliasing 1.760s 136.691us 5 5 100.00
clkmgr_same_csr_outstanding 1.660s 170.292us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.900s 43.399us 5 5 100.00
clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
clkmgr_csr_aliasing 1.760s 136.691us 5 5 100.00
clkmgr_same_csr_outstanding 1.660s 170.292us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.100s 281.646us 5 5 100.00
clkmgr_tl_intg_err 4.040s 517.361us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.010s 634.884us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.010s 634.884us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.010s 634.884us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.010s 634.884us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.310s 1.033ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.040s 517.361us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.060s 2.360ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.460s 2.422ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.010s 634.884us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.930s 390.322us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.250s 179.448us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.220s 160.383us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.350s 204.720us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.480s 235.590us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.100s 281.646us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.260s 197.723us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.100s 281.646us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.970s 1.270ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 24.546m 218.390ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results