CLKMGR Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.600s 297.220us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.310s 221.283us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.110s 657.850us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.840s 77.682us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.160s 177.655us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
clkmgr_csr_aliasing 1.840s 77.682us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.040s 139.075us 50 50 100.00
V2 trans_enables clkmgr_trans 1.550s 227.113us 50 50 100.00
V2 extclk clkmgr_extclk 1.660s 302.166us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.130s 179.048us 50 50 100.00
V2 jitter clkmgr_smoke 1.600s 297.220us 50 50 100.00
V2 frequency clkmgr_frequency 19.300s 2.478ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.230s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.300s 2.478ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.356m 12.151ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.870s 100.559us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.340s 197.996us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.260s 540.781us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.260s 540.781us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.310s 221.283us 5 5 100.00
clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
clkmgr_csr_aliasing 1.840s 77.682us 5 5 100.00
clkmgr_same_csr_outstanding 1.890s 211.313us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.310s 221.283us 5 5 100.00
clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
clkmgr_csr_aliasing 1.840s 77.682us 5 5 100.00
clkmgr_same_csr_outstanding 1.890s 211.313us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.620s 581.269us 5 5 100.00
clkmgr_tl_intg_err 5.300s 1.210ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.900s 474.194us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.900s 474.194us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.900s 474.194us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.900s 474.194us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.520s 1.349ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.300s 1.210ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.300s 2.478ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.230s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.900s 474.194us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.960s 387.339us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.790s 357.515us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.640s 308.696us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.120s 429.354us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.510s 244.652us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.620s 581.269us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.080s 177.485us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.620s 581.269us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.520s 1.251ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 29.991m 512.314ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results