CLKMGR Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.650s	313.900us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.910s	64.572us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.410s	816.723us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.250s	249.001us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.500s	487.192us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
		clkmgr_csr_aliasing	2.250s	249.001us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.100s	150.443us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.710s	657.118us	50	50	100.00
V2	extclk	clkmgr_extclk	2.000s	408.601us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.930s	110.449us	50	50	100.00
V2	jitter	clkmgr_smoke	1.650s	313.900us	50	50	100.00
V2	frequency	clkmgr_frequency	19.530s	2.476ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.760s	2.422ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.530s	2.476ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.535m	13.175ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	109.732us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.480s	249.620us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.590s	407.341us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.590s	407.341us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.910s	64.572us	5	5	100.00
		clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
		clkmgr_csr_aliasing	2.250s	249.001us	5	5	100.00
		clkmgr_same_csr_outstanding	2.670s	566.147us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.910s	64.572us	5	5	100.00
		clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
		clkmgr_csr_aliasing	2.250s	249.001us	5	5	100.00
		clkmgr_same_csr_outstanding	2.670s	566.147us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	9.360s	2.608ms	5	5	100.00
		clkmgr_tl_intg_err	3.940s	702.179us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	5.120s	1.448ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	5.120s	1.448ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	5.120s	1.448ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	5.120s	1.448ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.900s	522.015us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.940s	702.179us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.530s	2.476ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.760s	2.422ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	5.120s	1.448ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.850s	297.655us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	2.030s	385.420us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.690s	320.607us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.670s	302.561us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.900s	375.156us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	9.360s	2.608ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.070s	61.603us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	9.360s	2.608ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.940s	1.224ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	25.491m	334.523ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.88	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:752) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 17.clkmgr_stress_all_with_rand_reset.100069973804430388694427819575065089298542664674696292066398802569460433548627
      Line 1054, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23697462874 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 23697462874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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