CLKMGR Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.120s	125.505us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.870s	24.829us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	12.130s	1.988ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.100s	396.764us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.070s	47.394us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
		clkmgr_csr_aliasing	2.100s	396.764us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.170s	174.938us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.320s	152.375us	50	50	100.00
V2	extclk	clkmgr_extclk	1.600s	254.752us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.060s	170.042us	50	50	100.00
V2	jitter	clkmgr_smoke	1.120s	125.505us	50	50	100.00
V2	frequency	clkmgr_frequency	18.950s	2.484ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	13.710s	2.183ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.950s	2.484ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.617m	13.983ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.870s	94.573us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.600s	296.972us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.420s	379.700us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.420s	379.700us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.870s	24.829us	5	5	100.00
		clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
		clkmgr_csr_aliasing	2.100s	396.764us	5	5	100.00
		clkmgr_same_csr_outstanding	3.080s	754.601us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.870s	24.829us	5	5	100.00
		clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
		clkmgr_csr_aliasing	2.100s	396.764us	5	5	100.00
		clkmgr_same_csr_outstanding	3.080s	754.601us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.460s	1.200ms	5	5	100.00
		clkmgr_tl_intg_err	4.050s	732.066us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.770s	373.997us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.770s	373.997us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.770s	373.997us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.770s	373.997us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.840s	560.722us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.050s	732.066us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.950s	2.484ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	13.710s	2.183ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.770s	373.997us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.990s	323.702us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.770s	357.078us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.360s	221.927us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.380s	173.920us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.380s	212.699us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.460s	1.200ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.140s	193.447us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.460s	1.200ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.930s	1.117ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	25.854m	315.811ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.49	99.15	95.68	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))' has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 29.clkmgr_stress_all_with_rand_reset.1405355758065694363234622612684870731625335484070704653566670081003567198283
      Line 487, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'
        UVM_ERROR @ 25941942761 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A
        UVM_INFO @ 25941942761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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