CLKMGR Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.520s 246.756us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.860s 26.532us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 22.820s 6.968ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.930s 225.088us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.770s 75.727us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
clkmgr_csr_aliasing 1.930s 225.088us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.050s 116.987us 50 50 100.00
V2 trans_enables clkmgr_trans 1.370s 133.930us 50 50 100.00
V2 extclk clkmgr_extclk 1.300s 101.695us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.190s 199.204us 50 50 100.00
V2 jitter clkmgr_smoke 1.520s 246.756us 50 50 100.00
V2 frequency clkmgr_frequency 16.730s 2.240ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.870s 2.418ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 16.730s 2.240ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.209m 10.087ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.990s 141.168us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.280s 162.951us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.220s 1.280ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.220s 1.280ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.860s 26.532us 5 5 100.00
clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
clkmgr_csr_aliasing 1.930s 225.088us 5 5 100.00
clkmgr_same_csr_outstanding 1.730s 154.139us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.860s 26.532us 5 5 100.00
clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
clkmgr_csr_aliasing 1.930s 225.088us 5 5 100.00
clkmgr_same_csr_outstanding 1.730s 154.139us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.440s 439.275us 5 5 100.00
clkmgr_tl_intg_err 3.390s 558.435us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.010s 698.631us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.010s 698.631us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.010s 698.631us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.010s 698.631us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.320s 190.067us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.390s 558.435us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 16.730s 2.240ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.870s 2.418ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.010s 698.631us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.490s 212.983us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.770s 336.452us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.200s 160.004us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.140s 84.338us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.850s 339.972us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.440s 439.275us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.010s 66.055us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.440s 439.275us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.970s 1.399ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 37.925m 635.661ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results