CLKMGR Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.240s 153.690us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.900s 50.451us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.550s 1.382ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.280s 264.920us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.220s 492.996us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
clkmgr_csr_aliasing 2.280s 264.920us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.110s 146.472us 50 50 100.00
V2 trans_enables clkmgr_trans 1.470s 215.479us 50 50 100.00
V2 extclk clkmgr_extclk 1.930s 370.972us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.220s 218.067us 50 50 100.00
V2 jitter clkmgr_smoke 1.240s 153.690us 50 50 100.00
V2 frequency clkmgr_frequency 18.110s 2.481ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.260s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.110s 2.481ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.265m 11.011ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.860s 102.289us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.170s 126.143us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.420s 1.333ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.420s 1.333ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.900s 50.451us 5 5 100.00
clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
clkmgr_csr_aliasing 2.280s 264.920us 5 5 100.00
clkmgr_same_csr_outstanding 2.350s 461.663us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.900s 50.451us 5 5 100.00
clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
clkmgr_csr_aliasing 2.280s 264.920us 5 5 100.00
clkmgr_same_csr_outstanding 2.350s 461.663us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.020s 957.964us 5 5 100.00
clkmgr_tl_intg_err 5.220s 1.224ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.710s 378.979us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.710s 378.979us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.710s 378.979us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.710s 378.979us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.240s 422.412us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.220s 1.224ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.110s 2.481ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.260s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.710s 378.979us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.550s 208.937us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.950s 411.894us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.170s 155.698us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.710s 224.335us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.380s 185.333us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.020s 957.964us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.220s 234.617us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.020s 957.964us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.610s 1.289ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 45.711m 678.622ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results