V1 |
smoke |
clkmgr_smoke |
1.400s |
235.853us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
clkmgr_csr_hw_reset |
1.010s |
101.589us |
5 |
5 |
100.00 |
V1 |
csr_rw |
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
clkmgr_csr_bit_bash |
8.110s |
578.289us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
clkmgr_csr_aliasing |
2.040s |
207.921us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
clkmgr_csr_mem_rw_with_rand_reset |
2.270s |
439.635us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.040s |
207.921us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
peri_enables |
clkmgr_peri |
0.950s |
83.107us |
50 |
50 |
100.00 |
V2 |
trans_enables |
clkmgr_trans |
2.520s |
516.565us |
50 |
50 |
100.00 |
V2 |
extclk |
clkmgr_extclk |
1.270s |
167.294us |
50 |
50 |
100.00 |
V2 |
clk_status |
clkmgr_clk_status |
1.270s |
227.068us |
50 |
50 |
100.00 |
V2 |
jitter |
clkmgr_smoke |
1.400s |
235.853us |
50 |
50 |
100.00 |
V2 |
frequency |
clkmgr_frequency |
18.730s |
2.480ms |
50 |
50 |
100.00 |
V2 |
frequency_timeout |
clkmgr_frequency_timeout |
15.960s |
2.421ms |
50 |
50 |
100.00 |
V2 |
frequency_overflow |
clkmgr_frequency |
18.730s |
2.480ms |
50 |
50 |
100.00 |
V2 |
stress_all |
clkmgr_stress_all |
1.619m |
12.983ms |
50 |
50 |
100.00 |
V2 |
intr_test |
clkmgr_intr_test |
0.820s |
98.285us |
50 |
50 |
100.00 |
V2 |
alert_test |
clkmgr_alert_test |
1.020s |
98.913us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
clkmgr_tl_errors |
7.390s |
1.682ms |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
clkmgr_tl_errors |
7.390s |
1.682ms |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
clkmgr_csr_hw_reset |
1.010s |
101.589us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.040s |
207.921us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.790s |
259.493us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
clkmgr_csr_hw_reset |
1.010s |
101.589us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.040s |
207.921us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.790s |
259.493us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
490 |
490 |
100.00 |
V2S |
tl_intg_err |
clkmgr_sec_cm |
3.860s |
486.066us |
5 |
5 |
100.00 |
|
|
clkmgr_tl_intg_err |
3.900s |
737.409us |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error |
clkmgr_shadow_reg_errors |
4.180s |
1.077ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_read_clear_staged_value |
clkmgr_shadow_reg_errors |
4.180s |
1.077ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_storage_error |
clkmgr_shadow_reg_errors |
4.180s |
1.077ms |
20 |
20 |
100.00 |
V2S |
shadowed_reset_glitch |
clkmgr_shadow_reg_errors |
4.180s |
1.077ms |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error_with_csr_rw |
clkmgr_shadow_reg_errors_with_csr_rw |
3.910s |
593.421us |
20 |
20 |
100.00 |
V2S |
sec_cm_bus_integrity |
clkmgr_tl_intg_err |
3.900s |
737.409us |
20 |
20 |
100.00 |
V2S |
sec_cm_meas_clk_bkgn_chk |
clkmgr_frequency |
18.730s |
2.480ms |
50 |
50 |
100.00 |
V2S |
sec_cm_timeout_clk_bkgn_chk |
clkmgr_frequency_timeout |
15.960s |
2.421ms |
50 |
50 |
100.00 |
V2S |
sec_cm_meas_config_shadow |
clkmgr_shadow_reg_errors |
4.180s |
1.077ms |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_intersig_mubi |
clkmgr_idle_intersig_mubi |
1.840s |
340.072us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_intersig_mubi |
clkmgr_lc_ctrl_intersig_mubi |
1.570s |
279.760us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_clk_handshake_intersig_mubi |
clkmgr_lc_clk_byp_req_intersig_mubi |
1.580s |
289.805us |
50 |
50 |
100.00 |
V2S |
sec_cm_clk_handshake_intersig_mubi |
clkmgr_clk_handshake_intersig_mubi |
1.590s |
255.070us |
50 |
50 |
100.00 |
V2S |
sec_cm_div_intersig_mubi |
clkmgr_div_intersig_mubi |
1.700s |
318.861us |
50 |
50 |
100.00 |
V2S |
sec_cm_jitter_config_mubi |
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_ctr_redun |
clkmgr_sec_cm |
3.860s |
486.066us |
5 |
5 |
100.00 |
V2S |
sec_cm_meas_config_regwen |
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
V2S |
sec_cm_clk_ctrl_config_regwen |
clkmgr_csr_rw |
0.960s |
75.931us |
20 |
20 |
100.00 |
V2S |
prim_count_check |
clkmgr_sec_cm |
3.860s |
486.066us |
5 |
5 |
100.00 |
V2S |
|
TOTAL |
|
|
315 |
315 |
100.00 |
V3 |
regwen |
clkmgr_regwen |
7.750s |
1.426ms |
50 |
50 |
100.00 |
V3 |
stress_all_with_rand_reset |
clkmgr_stress_all_with_rand_reset |
23.949m |
228.643ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
100 |
100 |
100.00 |
|
|
TOTAL |
|
|
1010 |
1010 |
100.00 |