V1 |
smoke |
clkmgr_smoke |
1.150s |
136.210us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
clkmgr_csr_hw_reset |
1.140s |
128.958us |
5 |
5 |
100.00 |
V1 |
csr_rw |
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
clkmgr_csr_bit_bash |
5.060s |
495.995us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
clkmgr_csr_aliasing |
2.310s |
265.940us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
clkmgr_csr_mem_rw_with_rand_reset |
2.200s |
127.782us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.310s |
265.940us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
peri_enables |
clkmgr_peri |
1.060s |
123.446us |
50 |
50 |
100.00 |
V2 |
trans_enables |
clkmgr_trans |
2.760s |
636.504us |
50 |
50 |
100.00 |
V2 |
extclk |
clkmgr_extclk |
1.380s |
197.500us |
50 |
50 |
100.00 |
V2 |
clk_status |
clkmgr_clk_status |
1.020s |
92.983us |
50 |
50 |
100.00 |
V2 |
jitter |
clkmgr_smoke |
1.150s |
136.210us |
50 |
50 |
100.00 |
V2 |
frequency |
clkmgr_frequency |
18.020s |
2.360ms |
50 |
50 |
100.00 |
V2 |
frequency_timeout |
clkmgr_frequency_timeout |
18.300s |
2.419ms |
50 |
50 |
100.00 |
V2 |
frequency_overflow |
clkmgr_frequency |
18.020s |
2.360ms |
50 |
50 |
100.00 |
V2 |
stress_all |
clkmgr_stress_all |
1.395m |
12.159ms |
50 |
50 |
100.00 |
V2 |
intr_test |
clkmgr_intr_test |
0.880s |
99.864us |
50 |
50 |
100.00 |
V2 |
alert_test |
clkmgr_alert_test |
1.200s |
105.721us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
clkmgr_tl_errors |
4.950s |
1.259ms |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
clkmgr_tl_errors |
4.950s |
1.259ms |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
clkmgr_csr_hw_reset |
1.140s |
128.958us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.310s |
265.940us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.930s |
471.947us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
clkmgr_csr_hw_reset |
1.140s |
128.958us |
5 |
5 |
100.00 |
|
|
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
|
|
clkmgr_csr_aliasing |
2.310s |
265.940us |
5 |
5 |
100.00 |
|
|
clkmgr_same_csr_outstanding |
1.930s |
471.947us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
490 |
490 |
100.00 |
V2S |
tl_intg_err |
clkmgr_sec_cm |
3.650s |
566.649us |
5 |
5 |
100.00 |
|
|
clkmgr_tl_intg_err |
3.600s |
580.852us |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error |
clkmgr_shadow_reg_errors |
2.500s |
417.908us |
20 |
20 |
100.00 |
V2S |
shadow_reg_read_clear_staged_value |
clkmgr_shadow_reg_errors |
2.500s |
417.908us |
20 |
20 |
100.00 |
V2S |
shadow_reg_storage_error |
clkmgr_shadow_reg_errors |
2.500s |
417.908us |
20 |
20 |
100.00 |
V2S |
shadowed_reset_glitch |
clkmgr_shadow_reg_errors |
2.500s |
417.908us |
20 |
20 |
100.00 |
V2S |
shadow_reg_update_error_with_csr_rw |
clkmgr_shadow_reg_errors_with_csr_rw |
4.380s |
1.146ms |
20 |
20 |
100.00 |
V2S |
sec_cm_bus_integrity |
clkmgr_tl_intg_err |
3.600s |
580.852us |
20 |
20 |
100.00 |
V2S |
sec_cm_meas_clk_bkgn_chk |
clkmgr_frequency |
18.020s |
2.360ms |
50 |
50 |
100.00 |
V2S |
sec_cm_timeout_clk_bkgn_chk |
clkmgr_frequency_timeout |
18.300s |
2.419ms |
50 |
50 |
100.00 |
V2S |
sec_cm_meas_config_shadow |
clkmgr_shadow_reg_errors |
2.500s |
417.908us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_intersig_mubi |
clkmgr_idle_intersig_mubi |
1.950s |
344.323us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_intersig_mubi |
clkmgr_lc_ctrl_intersig_mubi |
1.380s |
179.008us |
50 |
50 |
100.00 |
V2S |
sec_cm_lc_ctrl_clk_handshake_intersig_mubi |
clkmgr_lc_clk_byp_req_intersig_mubi |
1.120s |
135.671us |
50 |
50 |
100.00 |
V2S |
sec_cm_clk_handshake_intersig_mubi |
clkmgr_clk_handshake_intersig_mubi |
1.680s |
293.753us |
50 |
50 |
100.00 |
V2S |
sec_cm_div_intersig_mubi |
clkmgr_div_intersig_mubi |
1.320s |
192.703us |
50 |
50 |
100.00 |
V2S |
sec_cm_jitter_config_mubi |
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
V2S |
sec_cm_idle_ctr_redun |
clkmgr_sec_cm |
3.650s |
566.649us |
5 |
5 |
100.00 |
V2S |
sec_cm_meas_config_regwen |
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
V2S |
sec_cm_clk_ctrl_config_regwen |
clkmgr_csr_rw |
1.290s |
208.041us |
20 |
20 |
100.00 |
V2S |
prim_count_check |
clkmgr_sec_cm |
3.650s |
566.649us |
5 |
5 |
100.00 |
V2S |
|
TOTAL |
|
|
315 |
315 |
100.00 |
V3 |
regwen |
clkmgr_regwen |
6.640s |
1.581ms |
50 |
50 |
100.00 |
V3 |
stress_all_with_rand_reset |
clkmgr_stress_all_with_rand_reset |
36.365m |
459.542ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
100 |
100 |
100.00 |
|
|
TOTAL |
|
|
1010 |
1010 |
100.00 |