CLKMGR Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.560s 258.346us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.870s 47.719us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 12.380s 2.213ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.840s 108.002us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.870s 36.524us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
clkmgr_csr_aliasing 1.840s 108.002us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.900s 52.570us 50 50 100.00
V2 trans_enables clkmgr_trans 1.930s 421.399us 50 50 100.00
V2 extclk clkmgr_extclk 1.540s 261.473us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.880s 66.393us 50 50 100.00
V2 jitter clkmgr_smoke 1.560s 258.346us 50 50 100.00
V2 frequency clkmgr_frequency 18.410s 2.357ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.810s 2.175ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.410s 2.357ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.398m 11.274ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.940s 115.294us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.260s 149.383us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.640s 1.162ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.640s 1.162ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.870s 47.719us 5 5 100.00
clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
clkmgr_csr_aliasing 1.840s 108.002us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 316.228us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.870s 47.719us 5 5 100.00
clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
clkmgr_csr_aliasing 1.840s 108.002us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 316.228us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.590s 523.594us 5 5 100.00
clkmgr_tl_intg_err 6.400s 1.672ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.050s 656.418us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.050s 656.418us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.050s 656.418us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.050s 656.418us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.800s 1.965ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 6.400s 1.672ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.410s 2.357ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.810s 2.175ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.050s 656.418us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.430s 495.495us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.630s 307.745us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.240s 175.874us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.700s 287.242us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.770s 300.730us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.590s 523.594us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.330s 218.887us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.590s 523.594us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.750s 1.132ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 24.584m 238.551ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results