CLKMGR Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.530s 267.870us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.060s 133.550us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 13.210s 1.938ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.350s 467.590us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.280s 69.219us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
clkmgr_csr_aliasing 2.350s 467.590us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.050s 114.588us 50 50 100.00
V2 trans_enables clkmgr_trans 1.860s 371.678us 50 50 100.00
V2 extclk clkmgr_extclk 1.620s 242.152us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.150s 179.992us 50 50 100.00
V2 jitter clkmgr_smoke 1.530s 267.870us 50 50 100.00
V2 frequency clkmgr_frequency 19.350s 2.482ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.180s 2.297ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.350s 2.482ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.323m 10.793ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.010s 136.501us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.190s 146.095us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.860s 1.369ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.860s 1.369ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.060s 133.550us 5 5 100.00
clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
clkmgr_csr_aliasing 2.350s 467.590us 5 5 100.00
clkmgr_same_csr_outstanding 2.010s 271.104us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.060s 133.550us 5 5 100.00
clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
clkmgr_csr_aliasing 2.350s 467.590us 5 5 100.00
clkmgr_same_csr_outstanding 2.010s 271.104us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.640s 1.201ms 5 5 100.00
clkmgr_tl_intg_err 5.690s 1.165ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.340s 629.086us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.340s 629.086us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.340s 629.086us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.340s 629.086us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.290s 648.717us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.690s 1.165ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.350s 2.482ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.180s 2.297ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.340s 629.086us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.050s 410.073us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.740s 299.724us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.610s 243.392us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.660s 274.917us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.340s 154.159us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.640s 1.201ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.280s 219.220us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.640s 1.201ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.520s 1.290ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 27.308m 446.246ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.11 95.68 100.00 100.00 98.71 97.02 98.80

Past Results