CLKMGR Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.550s	234.852us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	58.239us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	16.710s	3.665ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.980s	105.799us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.380s	138.640us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
		clkmgr_csr_aliasing	1.980s	105.799us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.060s	138.830us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.420s	239.113us	50	50	100.00
V2	extclk	clkmgr_extclk	1.140s	87.521us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.990s	127.562us	50	50	100.00
V2	jitter	clkmgr_smoke	1.550s	234.852us	50	50	100.00
V2	frequency	clkmgr_frequency	16.950s	2.237ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.950s	2.300ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.950s	2.237ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	2.099m	18.096ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.900s	85.241us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.250s	174.322us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.030s	1.033ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.030s	1.033ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	58.239us	5	5	100.00
		clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
		clkmgr_csr_aliasing	1.980s	105.799us	5	5	100.00
		clkmgr_same_csr_outstanding	1.810s	354.422us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	58.239us	5	5	100.00
		clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
		clkmgr_csr_aliasing	1.980s	105.799us	5	5	100.00
		clkmgr_same_csr_outstanding	1.810s	354.422us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	7.420s	2.076ms	5	5	100.00
		clkmgr_tl_intg_err	3.800s	770.274us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.000s	562.431us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.000s	562.431us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.000s	562.431us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.000s	562.431us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.960s	1.363ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.800s	770.274us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.950s	2.237ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.950s	2.300ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.000s	562.431us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.490s	149.479us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.220s	158.114us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.410s	194.466us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.870s	331.863us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.410s	215.414us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	7.420s	2.076ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.090s	185.811us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	7.420s	2.076ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.550s	1.405ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	51.914m	848.524ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:752) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 30.clkmgr_stress_all_with_rand_reset.17878392853272428404194620850699119311895683466368769215145583091138165410987
      Line 961, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22941620254 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 22941620254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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