CLKMGR Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.710s 319.756us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.890s 23.572us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 18.560s 4.705ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.960s 554.442us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.420s 168.239us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
clkmgr_csr_aliasing 2.960s 554.442us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.120s 131.421us 50 50 100.00
V2 trans_enables clkmgr_trans 1.860s 364.333us 50 50 100.00
V2 extclk clkmgr_extclk 1.330s 221.623us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.080s 162.682us 50 50 100.00
V2 jitter clkmgr_smoke 1.710s 319.756us 50 50 100.00
V2 frequency clkmgr_frequency 19.540s 2.476ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.870s 2.302ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.540s 2.476ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.164m 9.600ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.970s 145.073us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.280s 180.740us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.330s 686.034us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.330s 686.034us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.890s 23.572us 5 5 100.00
clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
clkmgr_csr_aliasing 2.960s 554.442us 5 5 100.00
clkmgr_same_csr_outstanding 2.890s 657.408us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.890s 23.572us 5 5 100.00
clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
clkmgr_csr_aliasing 2.960s 554.442us 5 5 100.00
clkmgr_same_csr_outstanding 2.890s 657.408us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.010s 764.156us 5 5 100.00
clkmgr_tl_intg_err 5.730s 1.290ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.930s 386.595us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.930s 386.595us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.930s 386.595us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.930s 386.595us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.410s 1.171ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.730s 1.290ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.540s 2.476ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.870s 2.302ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.930s 386.595us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.660s 267.651us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.290s 184.577us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 2.060s 419.438us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.890s 352.406us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.710s 314.322us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.010s 764.156us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.060s 75.690us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.010s 764.156us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.640s 1.410ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 25.892m 404.130ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results