CLKMGR Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.080s 68.651us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.870s 18.015us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.180s 1.004ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.940s 126.747us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.940s 40.244us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
clkmgr_csr_aliasing 1.940s 126.747us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.230s 175.040us 50 50 100.00
V2 trans_enables clkmgr_trans 1.930s 374.750us 50 50 100.00
V2 extclk clkmgr_extclk 1.230s 127.054us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.960s 110.043us 50 50 100.00
V2 jitter clkmgr_smoke 1.080s 68.651us 50 50 100.00
V2 frequency clkmgr_frequency 19.590s 2.474ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.720s 2.414ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.590s 2.474ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.480m 12.438ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.880s 101.734us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.990s 63.087us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.020s 1.060ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.020s 1.060ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.870s 18.015us 5 5 100.00
clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
clkmgr_csr_aliasing 1.940s 126.747us 5 5 100.00
clkmgr_same_csr_outstanding 2.150s 327.332us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.870s 18.015us 5 5 100.00
clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
clkmgr_csr_aliasing 1.940s 126.747us 5 5 100.00
clkmgr_same_csr_outstanding 2.150s 327.332us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.950s 653.899us 5 5 100.00
clkmgr_tl_intg_err 3.350s 351.355us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.700s 415.357us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.700s 415.357us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.700s 415.357us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.700s 415.357us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.520s 1.410ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.350s 351.355us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.590s 2.474ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.720s 2.414ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.700s 415.357us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.340s 131.665us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.640s 248.628us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.400s 203.113us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.360s 182.023us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.040s 411.649us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.950s 653.899us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.290s 187.877us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.950s 653.899us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.820s 1.366ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 26.122m 332.962ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results