CLKMGR Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.470s 250.896us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.860s 30.866us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.660s 894.818us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.960s 196.760us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.830s 335.948us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
clkmgr_csr_aliasing 1.960s 196.760us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.950s 98.716us 50 50 100.00
V2 trans_enables clkmgr_trans 1.280s 116.792us 50 50 100.00
V2 extclk clkmgr_extclk 1.480s 223.837us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.050s 126.032us 50 50 100.00
V2 jitter clkmgr_smoke 1.470s 250.896us 50 50 100.00
V2 frequency clkmgr_frequency 18.440s 2.360ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.910s 2.422ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.440s 2.360ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.491m 12.388ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 73.524us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.040s 78.398us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.540s 939.366us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.540s 939.366us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.860s 30.866us 5 5 100.00
clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
clkmgr_csr_aliasing 1.960s 196.760us 5 5 100.00
clkmgr_same_csr_outstanding 2.000s 300.707us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.860s 30.866us 5 5 100.00
clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
clkmgr_csr_aliasing 1.960s 196.760us 5 5 100.00
clkmgr_same_csr_outstanding 2.000s 300.707us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 10.660s 2.436ms 5 5 100.00
clkmgr_tl_intg_err 3.460s 454.253us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.590s 398.546us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.590s 398.546us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.590s 398.546us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.590s 398.546us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.840s 560.339us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.460s 454.253us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.440s 2.360ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.910s 2.422ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.590s 398.546us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.310s 163.178us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.710s 336.771us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.340s 221.962us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.440s 216.228us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.730s 345.305us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 10.660s 2.436ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.080s 123.866us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 10.660s 2.436ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.280s 1.272ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 33.915m 505.866ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results