CLKMGR Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.330s 189.831us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.900s 17.819us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.400s 691.120us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 3.090s 569.823us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.440s 143.264us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
clkmgr_csr_aliasing 3.090s 569.823us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.010s 96.112us 50 50 100.00
V2 trans_enables clkmgr_trans 1.570s 239.276us 50 50 100.00
V2 extclk clkmgr_extclk 1.730s 307.835us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.900s 54.126us 50 50 100.00
V2 jitter clkmgr_smoke 1.330s 189.831us 50 50 100.00
V2 frequency clkmgr_frequency 18.680s 2.481ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.200s 2.177ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.680s 2.481ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.320m 19.556ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.860s 92.571us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.160s 161.153us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.970s 1.587ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.970s 1.587ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.900s 17.819us 5 5 100.00
clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
clkmgr_csr_aliasing 3.090s 569.823us 5 5 100.00
clkmgr_same_csr_outstanding 1.520s 61.278us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.900s 17.819us 5 5 100.00
clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
clkmgr_csr_aliasing 3.090s 569.823us 5 5 100.00
clkmgr_same_csr_outstanding 1.520s 61.278us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.860s 642.321us 5 5 100.00
clkmgr_tl_intg_err 3.570s 438.714us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.490s 339.628us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.490s 339.628us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.490s 339.628us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.490s 339.628us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 7.170s 1.900ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.570s 438.714us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.680s 2.481ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.200s 2.177ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.490s 339.628us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.360s 124.549us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.610s 285.029us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.320s 143.095us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.390s 206.023us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.320s 197.106us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.860s 642.321us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.030s 113.296us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.860s 642.321us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.760s 1.391ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 1.016h 1.084s 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.45 99.11 95.52 100.00 100.00 98.71 97.02 98.80

Past Results