CLKMGR Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.640s 285.778us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.080s 134.764us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.220s 649.906us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.580s 593.053us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.430s 286.528us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
clkmgr_csr_aliasing 2.580s 593.053us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.220s 172.998us 50 50 100.00
V2 trans_enables clkmgr_trans 1.330s 107.281us 50 50 100.00
V2 extclk clkmgr_extclk 1.260s 163.563us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.030s 157.715us 50 50 100.00
V2 jitter clkmgr_smoke 1.640s 285.778us 50 50 100.00
V2 frequency clkmgr_frequency 18.090s 2.359ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.710s 2.421ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.090s 2.359ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.621m 13.316ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.030s 138.243us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.150s 136.581us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.020s 479.939us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.020s 479.939us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.080s 134.764us 5 5 100.00
clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
clkmgr_csr_aliasing 2.580s 593.053us 5 5 100.00
clkmgr_same_csr_outstanding 2.270s 434.880us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.080s 134.764us 5 5 100.00
clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
clkmgr_csr_aliasing 2.580s 593.053us 5 5 100.00
clkmgr_same_csr_outstanding 2.270s 434.880us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 7.790s 1.525ms 5 5 100.00
clkmgr_tl_intg_err 4.670s 904.861us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.800s 495.288us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.800s 495.288us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.800s 495.288us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.800s 495.288us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 7.380s 1.922ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.670s 904.861us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.090s 2.359ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.710s 2.421ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.800s 495.288us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.040s 403.229us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.350s 197.965us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.460s 220.405us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.170s 94.803us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.760s 309.314us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 7.790s 1.525ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.000s 121.967us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 7.790s 1.525ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.850s 1.390ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 24.325m 132.233ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results