CLKMGR Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.370s 176.244us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.870s 45.141us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 8.810s 2.173ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.780s 59.880us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.840s 90.524us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
clkmgr_csr_aliasing 1.780s 59.880us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.280s 193.360us 50 50 100.00
V2 trans_enables clkmgr_trans 1.370s 131.665us 50 50 100.00
V2 extclk clkmgr_extclk 1.260s 105.269us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.930s 104.751us 50 50 100.00
V2 jitter clkmgr_smoke 1.370s 176.244us 50 50 100.00
V2 frequency clkmgr_frequency 17.350s 2.239ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.720s 2.416ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.350s 2.239ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.531m 13.449ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 99.333us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.060s 73.024us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.420s 1.120ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.420s 1.120ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.870s 45.141us 5 5 100.00
clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
clkmgr_csr_aliasing 1.780s 59.880us 5 5 100.00
clkmgr_same_csr_outstanding 2.180s 454.033us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.870s 45.141us 5 5 100.00
clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
clkmgr_csr_aliasing 1.780s 59.880us 5 5 100.00
clkmgr_same_csr_outstanding 2.180s 454.033us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.450s 1.389ms 5 5 100.00
clkmgr_tl_intg_err 4.270s 818.256us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.220s 619.223us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.220s 619.223us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.220s 619.223us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.220s 619.223us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.840s 637.690us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.270s 818.256us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.350s 2.239ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.720s 2.416ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.220s 619.223us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.860s 656.712us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.220s 128.864us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.820s 332.459us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.860s 327.253us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.420s 210.556us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.450s 1.389ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.070s 135.106us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.450s 1.389ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.150s 1.144ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 43.664m 715.590ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results