CLKMGR Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.890s	375.889us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.860s	48.798us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.820s	2.459ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	3.030s	628.649us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.740s	70.629us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
		clkmgr_csr_aliasing	3.030s	628.649us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.010s	97.284us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.520s	189.247us	50	50	100.00
V2	extclk	clkmgr_extclk	1.560s	237.045us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.140s	146.209us	50	50	100.00
V2	jitter	clkmgr_smoke	1.890s	375.889us	50	50	100.00
V2	frequency	clkmgr_frequency	19.440s	2.475ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.250s	2.415ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.440s	2.475ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.507m	12.843ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.990s	142.116us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.420s	225.826us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.910s	467.198us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.910s	467.198us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.860s	48.798us	5	5	100.00
		clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
		clkmgr_csr_aliasing	3.030s	628.649us	5	5	100.00
		clkmgr_same_csr_outstanding	2.010s	305.921us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.860s	48.798us	5	5	100.00
		clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
		clkmgr_csr_aliasing	3.030s	628.649us	5	5	100.00
		clkmgr_same_csr_outstanding	2.010s	305.921us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.710s	582.188us	5	5	100.00
		clkmgr_tl_intg_err	5.610s	1.266ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.660s	355.364us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.660s	355.364us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.660s	355.364us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.660s	355.364us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.780s	455.505us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.610s	1.266ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.440s	2.475ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.250s	2.415ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.660s	355.364us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.890s	360.820us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.440s	217.921us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.380s	165.878us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.410s	219.943us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.340s	186.131us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.710s	582.188us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.960s	57.201us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.710s	582.188us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.870s	2.367ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	20.326m	210.282ms	19	50	38.00
V3		TOTAL			69	100	69.00
		TOTAL			979	1010	96.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 19 failures:
  • Test clkmgr_stress_all_with_rand_reset has 19 failures.

    • 0.clkmgr_stress_all_with_rand_reset.115024365034740018306271477852573041518657694235016053473051506176390276142942
      Line 854, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14596264067 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 14596264067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.clkmgr_stress_all_with_rand_reset.25278239376895382227408397371569278074227486652575612960443284780696942537963
      Line 762, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15734714669 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 15734714669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 12 failures:
  • Test clkmgr_stress_all_with_rand_reset has 12 failures.

    • 2.clkmgr_stress_all_with_rand_reset.73222382584899969770178854783210192010880750848586345905283228303871729954358
      Line 491, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9910026546 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 9910026546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.clkmgr_stress_all_with_rand_reset.54059939468933243811850901884604667869637403401618540308497369744841055605334
      Line 890, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18017431121 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 18017431121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

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