CLKMGR Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.650s	305.246us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.920s	39.473us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	16.950s	3.659ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.720s	66.115us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.730s	33.537us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	66.115us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.250s	184.036us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.680s	306.768us	50	50	100.00
V2	extclk	clkmgr_extclk	1.240s	158.205us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.010s	135.005us	50	50	100.00
V2	jitter	clkmgr_smoke	1.650s	305.246us	50	50	100.00
V2	frequency	clkmgr_frequency	19.590s	2.481ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.310s	2.300ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.590s	2.481ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.586m	12.877ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.040s	166.536us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.750s	343.205us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.760s	770.680us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.760s	770.680us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.920s	39.473us	5	5	100.00
		clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	66.115us	5	5	100.00
		clkmgr_same_csr_outstanding	2.390s	389.688us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.920s	39.473us	5	5	100.00
		clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	66.115us	5	5	100.00
		clkmgr_same_csr_outstanding	2.390s	389.688us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.990s	416.966us	5	5	100.00
		clkmgr_tl_intg_err	3.680s	436.285us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	4.480s	1.169ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	4.480s	1.169ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	4.480s	1.169ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	4.480s	1.169ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.760s	472.753us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.680s	436.285us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.590s	2.481ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.310s	2.300ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	4.480s	1.169ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.360s	142.767us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.250s	141.513us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.680s	314.861us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.450s	214.609us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.480s	241.668us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.990s	416.966us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.020s	75.572us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.990s	416.966us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.860s	1.236ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	22.571m	196.052ms	19	50	38.00
V3		TOTAL			69	100	69.00
		TOTAL			979	1010	96.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 16 failures:
  • Test clkmgr_stress_all_with_rand_reset has 16 failures.

    • 3.clkmgr_stress_all_with_rand_reset.45465299594157083400587405514897185874971784995522002824380272101944595221378
      Line 305, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 929800729 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 929800729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.clkmgr_stress_all_with_rand_reset.99527778340064341569869228903054249616219261157995753425769224561373023483152
      Line 810, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35750160811 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 35750160811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 15 failures:
  • Test clkmgr_stress_all_with_rand_reset has 15 failures.

    • 2.clkmgr_stress_all_with_rand_reset.8360748627124123342045159214344158644654197782618547807036676002369014085396
      Line 610, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9365305177 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 9365305177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.clkmgr_stress_all_with_rand_reset.106800401830348597717026918664255232398893956695210312369998731888840448131845
      Line 902, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24784839074 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 24784839074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

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