CLKMGR Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.730s	322.655us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.940s	76.060us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.030s	431.242us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.010s	200.055us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.590s	127.484us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
		clkmgr_csr_aliasing	2.010s	200.055us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.170s	170.654us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.310s	412.911us	50	50	100.00
V2	extclk	clkmgr_extclk	1.720s	318.333us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.930s	106.511us	50	50	100.00
V2	jitter	clkmgr_smoke	1.730s	322.655us	50	50	100.00
V2	frequency	clkmgr_frequency	17.280s	2.239ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	13.700s	1.942ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.280s	2.239ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	57.340s	11.242ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.790s	40.919us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.090s	123.104us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.840s	603.156us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.840s	603.156us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.940s	76.060us	5	5	100.00
		clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
		clkmgr_csr_aliasing	2.010s	200.055us	5	5	100.00
		clkmgr_same_csr_outstanding	1.670s	224.978us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.940s	76.060us	5	5	100.00
		clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
		clkmgr_csr_aliasing	2.010s	200.055us	5	5	100.00
		clkmgr_same_csr_outstanding	1.670s	224.978us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.240s	319.887us	5	5	100.00
		clkmgr_tl_intg_err	6.510s	1.760ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.830s	709.998us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.830s	709.998us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.830s	709.998us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.830s	709.998us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.490s	403.195us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	6.510s	1.760ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.280s	2.239ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	13.700s	1.942ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.830s	709.998us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.330s	127.927us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.260s	150.684us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.230s	168.176us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.270s	190.341us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.530s	237.670us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.240s	319.887us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.080s	108.928us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.240s	319.887us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.570s	1.095ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.522m	384.932ms	21	50	42.00
V3		TOTAL			71	100	71.00
		TOTAL			981	1010	97.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 18 failures:
  • Test clkmgr_stress_all_with_rand_reset has 18 failures.

    • 0.clkmgr_stress_all_with_rand_reset.52205937257890619009225115444500831780376113758192916664093581041650792334653
      Line 352, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3746920802 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 3746920802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.clkmgr_stress_all_with_rand_reset.47096441481856813929691817492733913991406639959206311812535431355618671287321
      Line 592, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11422779377 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 11422779377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 11 failures:
  • Test clkmgr_stress_all_with_rand_reset has 11 failures.

    • 5.clkmgr_stress_all_with_rand_reset.23268942896682161659791220498258145964181515420383490778943448312657655316420
      Line 393, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 747932987 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 747932987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.clkmgr_stress_all_with_rand_reset.3654726771944915046464679304943647953953454135867185608117438477686777895788
      Line 380, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3810519705 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 3810519705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

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