CLKMGR Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.150s	106.839us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.000s	103.123us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.240s	2.185ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.040s	288.531us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.310s	299.416us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
		clkmgr_csr_aliasing	2.040s	288.531us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.210s	181.218us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.890s	314.680us	50	50	100.00
V2	extclk	clkmgr_extclk	1.540s	261.145us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.920s	75.794us	50	50	100.00
V2	jitter	clkmgr_smoke	1.150s	106.839us	50	50	100.00
V2	frequency	clkmgr_frequency	19.380s	2.483ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.890s	2.175ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.380s	2.483ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.127m	8.856ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.850s	108.124us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.170s	157.059us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.130s	584.040us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.130s	584.040us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.000s	103.123us	5	5	100.00
		clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
		clkmgr_csr_aliasing	2.040s	288.531us	5	5	100.00
		clkmgr_same_csr_outstanding	1.790s	194.246us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.000s	103.123us	5	5	100.00
		clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
		clkmgr_csr_aliasing	2.040s	288.531us	5	5	100.00
		clkmgr_same_csr_outstanding	1.790s	194.246us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.550s	442.264us	5	5	100.00
		clkmgr_tl_intg_err	3.610s	464.479us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.330s	358.708us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.330s	358.708us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.330s	358.708us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.330s	358.708us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.690s	472.228us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.610s	464.479us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.380s	2.483ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.890s	2.175ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.330s	358.708us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.240s	475.558us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.920s	367.118us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.250s	174.251us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.260s	113.138us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.660s	260.104us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.550s	442.264us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.930s	49.361us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.550s	442.264us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.480s	1.548ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	21.728m	357.926ms	15	50	30.00
V3		TOTAL			65	100	65.00
		TOTAL			975	1010	96.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	99.11	95.68	100.00	100.00	98.71	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 19 failures:
  • Test clkmgr_stress_all_with_rand_reset has 19 failures.

    • 1.clkmgr_stress_all_with_rand_reset.64755636110954818564688957958365131596247510441009606804202864767513480168945
      Line 1049, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 72465826817 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 72465826817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.clkmgr_stress_all_with_rand_reset.95984745876319488486478473033859995015349860090066130598456520290138664576126
      Line 699, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10897672936 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 10897672936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 16 failures:
  • Test clkmgr_stress_all_with_rand_reset has 16 failures.

    • 2.clkmgr_stress_all_with_rand_reset.70029247076834657098849712540498564280817818072824050627490451260610183808852
      Line 369, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3398231403 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 3398231403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_stress_all_with_rand_reset.49192995702900944516370411068999134887524668524138058126902248993877843376455
      Line 493, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 33128620348 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 33128620348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

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