CLKMGR Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.730s	318.280us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.880s	18.944us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	15.050s	3.628ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.610s	353.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.050s	225.471us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
		clkmgr_csr_aliasing	2.610s	353.354us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.100s	113.437us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.080s	352.272us	50	50	100.00
V2	extclk	clkmgr_extclk	1.830s	354.820us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.990s	123.694us	50	50	100.00
V2	jitter	clkmgr_smoke	1.730s	318.280us	50	50	100.00
V2	frequency	clkmgr_frequency	20.020s	2.481ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	18.330s	2.415ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	20.020s	2.481ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.163m	12.842ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.970s	145.991us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.640s	246.032us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.790s	1.195ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.790s	1.195ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.880s	18.944us	5	5	100.00
		clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
		clkmgr_csr_aliasing	2.610s	353.354us	5	5	100.00
		clkmgr_same_csr_outstanding	1.550s	159.979us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.880s	18.944us	5	5	100.00
		clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
		clkmgr_csr_aliasing	2.610s	353.354us	5	5	100.00
		clkmgr_same_csr_outstanding	1.550s	159.979us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.310s	762.449us	5	5	100.00
		clkmgr_tl_intg_err	4.210s	764.841us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.950s	872.723us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.950s	872.723us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.950s	872.723us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.950s	872.723us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.160s	841.053us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.210s	764.841us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	20.020s	2.481ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	18.330s	2.415ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.950s	872.723us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.650s	254.731us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.520s	194.286us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.750s	299.121us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.830s	331.896us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.360s	201.592us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.310s	762.449us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.170s	176.736us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.310s	762.449us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.190s	1.433ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	32.014m	499.488ms	19	50	38.00
V3		TOTAL			69	100	69.00
		TOTAL			979	1010	96.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 18 failures:
  • Test clkmgr_stress_all_with_rand_reset has 18 failures.

    • 3.clkmgr_stress_all_with_rand_reset.2977523442420376928412248946522145458163536679586537725472802093061557777291
      Line 990, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 87468041864 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 87468041864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.clkmgr_stress_all_with_rand_reset.96923869420726411919984241216242583079621123626892342460921639528942662579003
      Line 508, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10713865998 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 10713865998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 13 failures:
  • Test clkmgr_stress_all_with_rand_reset has 13 failures.

    • 1.clkmgr_stress_all_with_rand_reset.80940021892156825905538420001339315588762157911290055728798063048590480268973
      Line 440, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5223651217 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 5223651217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.clkmgr_stress_all_with_rand_reset.24021788672165764128441432013476012336851080652811652932311866823501048509711
      Line 569, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7911649305 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 7911649305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

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