CLKMGR Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.730s	337.724us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.920s	66.837us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.520s	556.189us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.820s	105.501us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.970s	106.205us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	105.501us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.110s	90.708us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.870s	315.883us	50	50	100.00
V2	extclk	clkmgr_extclk	1.480s	251.504us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.030s	150.718us	50	50	100.00
V2	jitter	clkmgr_smoke	1.730s	337.724us	50	50	100.00
V2	frequency	clkmgr_frequency	19.370s	2.482ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.530s	2.300ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.370s	2.482ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.546m	13.008ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.840s	96.005us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.330s	205.232us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.370s	558.023us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.370s	558.023us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.920s	66.837us	5	5	100.00
		clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	105.501us	5	5	100.00
		clkmgr_same_csr_outstanding	2.140s	448.536us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.920s	66.837us	5	5	100.00
		clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	105.501us	5	5	100.00
		clkmgr_same_csr_outstanding	2.140s	448.536us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.240s	292.445us	5	5	100.00
		clkmgr_tl_intg_err	5.300s	1.188ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.740s	357.574us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.740s	357.574us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.740s	357.574us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.740s	357.574us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.060s	1.039ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.300s	1.188ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.370s	2.482ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.530s	2.300ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.740s	357.574us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.880s	338.287us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.620s	297.591us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.570s	280.105us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.680s	245.262us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.450s	246.025us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.240s	292.445us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.890s	23.176us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.240s	292.445us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.250s	1.273ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	42.398m	744.507ms	16	50	32.00
V3		TOTAL			66	100	66.00
		TOTAL			976	1010	96.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.80	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 21 failures:
  • Test clkmgr_stress_all_with_rand_reset has 21 failures.

    • 2.clkmgr_stress_all_with_rand_reset.81701782881497224663596330283159459227238250527541810309706648541719447350305
      Line 508, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14658564843 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 14658564843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.clkmgr_stress_all_with_rand_reset.30211314673005650287971825796247362729366584166575166389265736230584764167355
      Line 351, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3716617534 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 3716617534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 13 failures:
  • Test clkmgr_stress_all_with_rand_reset has 13 failures.

    • 0.clkmgr_stress_all_with_rand_reset.43176311626327057044534911493709342172706331871185548468664216630896017096158
      Line 638, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 77034161277 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 77034161277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.clkmgr_stress_all_with_rand_reset.6021706112766145686031664238030060997446546223097623411480158366003809122083
      Line 1138, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58239720219 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 58239720219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

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