CLKMGR Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.530s	266.207us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.020s	114.170us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.530s	263.925us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.270s	475.628us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.800s	229.050us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
		clkmgr_csr_aliasing	2.270s	475.628us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.990s	73.772us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.570s	601.897us	50	50	100.00
V2	extclk	clkmgr_extclk	1.200s	101.326us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.000s	114.263us	50	50	100.00
V2	jitter	clkmgr_smoke	1.530s	266.207us	50	50	100.00
V2	frequency	clkmgr_frequency	19.580s	2.482ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.190s	2.418ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.580s	2.482ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.388m	11.948ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.840s	84.577us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.180s	152.964us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.680s	686.689us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.680s	686.689us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.020s	114.170us	5	5	100.00
		clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
		clkmgr_csr_aliasing	2.270s	475.628us	5	5	100.00
		clkmgr_same_csr_outstanding	2.830s	620.993us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.020s	114.170us	5	5	100.00
		clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
		clkmgr_csr_aliasing	2.270s	475.628us	5	5	100.00
		clkmgr_same_csr_outstanding	2.830s	620.993us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.910s	651.435us	5	5	100.00
		clkmgr_tl_intg_err	7.090s	1.737ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	4.350s	1.103ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	4.350s	1.103ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	4.350s	1.103ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	4.350s	1.103ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	6.660s	1.729ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	7.090s	1.737ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.580s	2.482ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.190s	2.418ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	4.350s	1.103ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.250s	455.284us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.450s	226.471us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.550s	252.736us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	2.010s	388.366us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.430s	222.164us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.910s	651.435us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.000s	76.509us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.910s	651.435us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.100s	1.335ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	33.745m	533.074ms	22	50	44.00
V3		TOTAL			72	100	72.00
		TOTAL			982	1010	97.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 17 failures:
  • Test clkmgr_stress_all_with_rand_reset has 17 failures.

    • 1.clkmgr_stress_all_with_rand_reset.37493691238481362107578629323717446957708865343175606163287261843743342906108
      Line 267, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 117624491 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 117624491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.clkmgr_stress_all_with_rand_reset.73092157251599507431545304905936367333824768487415406322802903848954005315777
      Line 924, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29909180941 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 29909180941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 11 failures:
  • Test clkmgr_stress_all_with_rand_reset has 11 failures.

    • 2.clkmgr_stress_all_with_rand_reset.84698050392359056749466723058994083388223027059642786261303695326506656421182
      Line 1582, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 79978959797 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 79978959797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.clkmgr_stress_all_with_rand_reset.66823973731855221040508375986649163353270790342885878741910194781507260592863
      Line 292, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 856484929 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 856484929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

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