CLKMGR Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.280s	162.750us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.950s	103.406us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.290s	536.410us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.530s	354.835us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.020s	237.594us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
		clkmgr_csr_aliasing	2.530s	354.835us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.400s	227.200us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.480s	534.909us	50	50	100.00
V2	extclk	clkmgr_extclk	1.350s	187.006us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.070s	159.948us	50	50	100.00
V2	jitter	clkmgr_smoke	1.280s	162.750us	50	50	100.00
V2	frequency	clkmgr_frequency	18.350s	2.356ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.410s	2.414ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.350s	2.356ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.535m	12.571ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.880s	83.061us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.110s	129.739us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.930s	1.137ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.930s	1.137ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.950s	103.406us	5	5	100.00
		clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
		clkmgr_csr_aliasing	2.530s	354.835us	5	5	100.00
		clkmgr_same_csr_outstanding	2.180s	439.627us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.950s	103.406us	5	5	100.00
		clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
		clkmgr_csr_aliasing	2.530s	354.835us	5	5	100.00
		clkmgr_same_csr_outstanding	2.180s	439.627us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	9.060s	2.300ms	5	5	100.00
		clkmgr_tl_intg_err	3.520s	646.386us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.150s	766.493us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.150s	766.493us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.150s	766.493us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.150s	766.493us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.850s	1.464ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.520s	646.386us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.350s	2.356ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.410s	2.414ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.150s	766.493us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.760s	278.532us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	2.010s	377.203us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.410s	225.941us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.720s	291.936us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.710s	303.316us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	9.060s	2.300ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.040s	82.487us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	9.060s	2.300ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.290s	1.474ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	25.058m	246.570ms	20	50	40.00
V3		TOTAL			70	100	70.00
		TOTAL			980	1010	97.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.76	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 16 failures:
  • Test clkmgr_stress_all_with_rand_reset has 16 failures.

    • 0.clkmgr_stress_all_with_rand_reset.58461839919579314966988188800256064831046289122594877483222718450777630400163
      Line 392, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2952237928 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 2952237928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_stress_all_with_rand_reset.93704239278469284490703669172243602206680928400413960654483570010596156366357
      Line 720, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17310431374 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 17310431374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 14 failures:
  • Test clkmgr_stress_all_with_rand_reset has 14 failures.

    • 1.clkmgr_stress_all_with_rand_reset.20418225952750499723069738930776131201902389187274993369616475038135659274158
      Line 507, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5352731733 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 5352731733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_stress_all_with_rand_reset.93392993921264871114019087317029338199984838203004258008735861840393767312282
      Line 409, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6219830870 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 6219830870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

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