CLKMGR Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.610s	251.885us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	123.398us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	11.770s	1.774ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.090s	409.330us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.520s	380.706us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
		clkmgr_csr_aliasing	2.090s	409.330us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.240s	177.186us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.570s	220.362us	50	50	100.00
V2	extclk	clkmgr_extclk	2.040s	430.351us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.990s	107.978us	50	50	100.00
V2	jitter	clkmgr_smoke	1.610s	251.885us	50	50	100.00
V2	frequency	clkmgr_frequency	18.790s	2.476ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.980s	2.298ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.790s	2.476ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.525m	12.543ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.840s	90.473us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.720s	322.041us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.890s	410.295us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.890s	410.295us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	123.398us	5	5	100.00
		clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
		clkmgr_csr_aliasing	2.090s	409.330us	5	5	100.00
		clkmgr_same_csr_outstanding	2.440s	474.642us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	123.398us	5	5	100.00
		clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
		clkmgr_csr_aliasing	2.090s	409.330us	5	5	100.00
		clkmgr_same_csr_outstanding	2.440s	474.642us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.500s	748.014us	5	5	100.00
		clkmgr_tl_intg_err	5.680s	1.359ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.290s	791.169us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.290s	791.169us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.290s	791.169us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.290s	791.169us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.540s	779.991us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.680s	1.359ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.790s	2.476ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.980s	2.298ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.290s	791.169us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.340s	492.221us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.360s	169.204us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.390s	199.989us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.750s	315.377us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	2.110s	439.545us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.500s	748.014us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.140s	137.828us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.500s	748.014us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.090s	1.204ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	51.456m	858.035ms	15	50	30.00
V3		TOTAL			65	100	65.00
		TOTAL			975	1010	96.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 20 failures:
  • Test clkmgr_stress_all_with_rand_reset has 20 failures.

    • 1.clkmgr_stress_all_with_rand_reset.33202926907204602331371970698310648108723087515076089501513821964108120649670
      Line 602, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8712640186 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 8712640186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_stress_all_with_rand_reset.49731329358236934955768930982389629691598446006360466614210524398195245822678
      Line 458, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 55839873449 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 55839873449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 15 failures:
  • Test clkmgr_stress_all_with_rand_reset has 15 failures.

    • 0.clkmgr_stress_all_with_rand_reset.13467999700301055093524673549567295617175645062135602749925233180219238987200
      Line 395, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19958165482 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 19958165482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.clkmgr_stress_all_with_rand_reset.60903109087335472586634044957120556029027574569659103926998751659578878231656
      Line 931, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8163724242 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 8163724242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

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