CLKMGR Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.490s	229.757us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.960s	97.866us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.590s	1.497ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.340s	117.050us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.320s	480.627us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
		clkmgr_csr_aliasing	1.340s	117.050us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.990s	110.468us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.310s	467.479us	50	50	100.00
V2	extclk	clkmgr_extclk	1.320s	215.718us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.090s	148.911us	50	50	100.00
V2	jitter	clkmgr_smoke	1.490s	229.757us	50	50	100.00
V2	frequency	clkmgr_frequency	19.200s	2.358ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	18.130s	2.421ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.200s	2.358ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.517m	12.408ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.070s	151.395us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.060s	113.799us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.930s	452.706us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.930s	452.706us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.960s	97.866us	5	5	100.00
		clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
		clkmgr_csr_aliasing	1.340s	117.050us	5	5	100.00
		clkmgr_same_csr_outstanding	1.980s	296.313us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.960s	97.866us	5	5	100.00
		clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
		clkmgr_csr_aliasing	1.340s	117.050us	5	5	100.00
		clkmgr_same_csr_outstanding	1.980s	296.313us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.030s	586.869us	5	5	100.00
		clkmgr_tl_intg_err	5.220s	1.263ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.510s	431.677us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.510s	431.677us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.510s	431.677us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.510s	431.677us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.400s	784.906us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.220s	1.263ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.200s	2.358ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	18.130s	2.421ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.510s	431.677us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.920s	679.962us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.380s	216.059us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.630s	257.538us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.810s	325.911us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.870s	365.458us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.030s	586.869us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.990s	74.988us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.030s	586.869us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.160s	1.404ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	27.247m	260.963ms	23	50	46.00
V3		TOTAL			73	100	73.00
		TOTAL			983	1010	97.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 17 failures:
  • Test clkmgr_stress_all_with_rand_reset has 17 failures.

    • 3.clkmgr_stress_all_with_rand_reset.20401686708539956016045298204541024781935637247288690609006469228042848686419
      Line 369, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1599476796 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 1599476796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.clkmgr_stress_all_with_rand_reset.27880853876428059977375756141054378260684460456876527359999745662176547167688
      Line 269, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 575093810 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 575093810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 10 failures:
  • Test clkmgr_stress_all_with_rand_reset has 10 failures.

    • 0.clkmgr_stress_all_with_rand_reset.47501285869984873337182375171430837978752990732421125137575864608183196686289
      Line 804, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28146082495 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 28146082495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_stress_all_with_rand_reset.77884968732821115353784923785249465016197403988110295051508843313632424635376
      Line 2145, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57422207440 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 57422207440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

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