CLKMGR Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.650s	323.509us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	73.881us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	21.890s	6.597ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.380s	261.345us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.710s	36.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
		clkmgr_csr_aliasing	2.380s	261.345us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.350s	180.435us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.120s	414.497us	50	50	100.00
V2	extclk	clkmgr_extclk	1.330s	165.681us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.040s	157.830us	50	50	100.00
V2	jitter	clkmgr_smoke	1.650s	323.509us	50	50	100.00
V2	frequency	clkmgr_frequency	20.160s	2.482ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.140s	2.293ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	20.160s	2.482ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.388m	11.574ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.890s	97.763us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.430s	211.815us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.740s	732.501us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.740s	732.501us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	73.881us	5	5	100.00
		clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
		clkmgr_csr_aliasing	2.380s	261.345us	5	5	100.00
		clkmgr_same_csr_outstanding	1.740s	195.603us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	73.881us	5	5	100.00
		clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
		clkmgr_csr_aliasing	2.380s	261.345us	5	5	100.00
		clkmgr_same_csr_outstanding	1.740s	195.603us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.070s	781.370us	5	5	100.00
		clkmgr_tl_intg_err	3.540s	538.214us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.370s	305.684us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.370s	305.684us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.370s	305.684us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.370s	305.684us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.730s	590.039us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.540s	538.214us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	20.160s	2.482ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.140s	2.293ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.370s	305.684us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.860s	669.454us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.610s	244.257us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.200s	128.714us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.520s	235.084us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.720s	324.069us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.070s	781.370us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.060s	142.322us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.070s	781.370us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.110s	1.348ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	45.504m	717.587ms	17	50	34.00
V3		TOTAL			67	100	67.00
		TOTAL			977	1010	96.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 22 failures:
  • Test clkmgr_stress_all_with_rand_reset has 22 failures.

    • 0.clkmgr_stress_all_with_rand_reset.78304322139905486946427242116571048161923504348488023469665127597897693857590
      Line 914, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 272266402712 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 272266402712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.clkmgr_stress_all_with_rand_reset.102387173419512074968008499328544906730138860010378141984364038682050111633458
      Line 289, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 449449356 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 449449356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 11 failures:
  • Test clkmgr_stress_all_with_rand_reset has 11 failures.

    • 4.clkmgr_stress_all_with_rand_reset.53701034293129265818987071375053889139002622985617840281451792648201418311519
      Line 335, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2278242705 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 2278242705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.clkmgr_stress_all_with_rand_reset.14110462634780736908628757090047204232255924262083224930288296345218884301911
      Line 1355, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 84553521446 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 84553521446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

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