CLKMGR Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.240s	175.565us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.870s	24.004us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.530s	1.373ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.700s	112.556us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.310s	323.299us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
		clkmgr_csr_aliasing	1.700s	112.556us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.940s	83.620us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.890s	371.709us	50	50	100.00
V2	extclk	clkmgr_extclk	1.720s	309.389us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.970s	111.000us	50	50	100.00
V2	jitter	clkmgr_smoke	1.240s	175.565us	50	50	100.00
V2	frequency	clkmgr_frequency	19.000s	2.356ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.200s	2.058ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.000s	2.356ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.616m	13.002ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.880s	78.578us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.150s	117.809us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.660s	584.468us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.660s	584.468us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.870s	24.004us	5	5	100.00
		clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
		clkmgr_csr_aliasing	1.700s	112.556us	5	5	100.00
		clkmgr_same_csr_outstanding	1.590s	227.452us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.870s	24.004us	5	5	100.00
		clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
		clkmgr_csr_aliasing	1.700s	112.556us	5	5	100.00
		clkmgr_same_csr_outstanding	1.590s	227.452us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.390s	783.080us	5	5	100.00
		clkmgr_tl_intg_err	3.480s	435.973us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.760s	660.850us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.760s	660.850us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.760s	660.850us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.760s	660.850us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.780s	472.523us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.480s	435.973us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.000s	2.356ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.200s	2.058ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.760s	660.850us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.800s	271.715us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.360s	168.058us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.420s	190.210us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.540s	250.332us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.460s	213.878us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.390s	783.080us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.980s	53.424us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.390s	783.080us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.080s	2.421ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	20.258m	174.022ms	23	50	46.00
V3		TOTAL			73	100	73.00
		TOTAL			983	1010	97.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 14 failures:
  • Test clkmgr_stress_all_with_rand_reset has 14 failures.

    • 3.clkmgr_stress_all_with_rand_reset.84606209765491358775951728605176662132599762111683200843481670071155155023709
      Line 1410, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 79872278588 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 79872278588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.clkmgr_stress_all_with_rand_reset.80315435964163820785789095984255671557636917150221906700872911140964818698981
      Line 431, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3175987771 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 3175987771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 13 failures:
  • Test clkmgr_stress_all_with_rand_reset has 13 failures.

    • 0.clkmgr_stress_all_with_rand_reset.101123059593945458481949802835391522118365882673939140389277344373980684854632
      Line 961, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37934380036 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 37934380036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_stress_all_with_rand_reset.78995399968341920572077599279374799659402664941902256085860575041730686337891
      Line 289, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2024228798 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 2024228798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

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