CLKMGR Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.180s	150.956us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.850s	45.014us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.720s	2.647ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.500s	37.596us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.950s	116.429us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
		clkmgr_csr_aliasing	1.500s	37.596us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.090s	131.878us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.570s	560.646us	50	50	100.00
V2	extclk	clkmgr_extclk	1.430s	239.860us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.050s	159.665us	50	50	100.00
V2	jitter	clkmgr_smoke	1.180s	150.956us	50	50	100.00
V2	frequency	clkmgr_frequency	18.460s	2.238ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.180s	2.297ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.460s	2.238ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.097m	8.954ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.910s	118.392us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.370s	223.082us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.070s	1.402ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.070s	1.402ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.850s	45.014us	5	5	100.00
		clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
		clkmgr_csr_aliasing	1.500s	37.596us	5	5	100.00
		clkmgr_same_csr_outstanding	1.470s	157.617us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.850s	45.014us	5	5	100.00
		clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
		clkmgr_csr_aliasing	1.500s	37.596us	5	5	100.00
		clkmgr_same_csr_outstanding	1.470s	157.617us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.790s	881.274us	5	5	100.00
		clkmgr_tl_intg_err	5.140s	684.986us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	4.210s	1.064ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	4.210s	1.064ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	4.210s	1.064ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	4.210s	1.064ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.900s	650.507us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.140s	684.986us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.460s	2.238ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.180s	2.297ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	4.210s	1.064ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.700s	324.364us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.320s	193.922us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.750s	327.110us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.560s	255.397us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.490s	237.812us	49	50	98.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.790s	881.274us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.080s	125.950us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.790s	881.274us	5	5	100.00
V2S		TOTAL			314	315	99.68
V3	regwen	clkmgr_regwen	6.590s	1.115ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.122m	253.822ms	19	50	38.00
V3		TOTAL			69	100	69.00
		TOTAL			978	1010	96.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	99.11	95.68	100.00	100.00	98.71	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 20 failures:
  • Test clkmgr_stress_all_with_rand_reset has 20 failures.

    • 0.clkmgr_stress_all_with_rand_reset.78976110528251550231543835312140931379914038937887216289879919940966654172573
      Line 845, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26539011977 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 26539011977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_stress_all_with_rand_reset.40714464896201503282764639408663901513296754513728693453765157989621563114150
      Line 696, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24350277803 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 24350277803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 11 failures:
  • Test clkmgr_stress_all_with_rand_reset has 11 failures.

    • 3.clkmgr_stress_all_with_rand_reset.72933820223294665300598298190278586167173254755249210720824605915805413259966
      Line 1050, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28480582072 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 28480582072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.clkmgr_stress_all_with_rand_reset.36576638865772733285918317422454329027639569446898244207649070721736551427423
      Line 710, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32824912492 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 32824912492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• Offending '(gen_flops.gen_stable_chks.sig_unstable || (mubi_o == {NumCopies {$past(gen_flops.gen_stable_chks.mubi_in_sva_q, *)}}))' has 1 failures:
  • Test clkmgr_div_intersig_mubi has 1 failures.

    • 44.clkmgr_div_intersig_mubi.48655389989445072448719894580760222053223196289007256658349660030272495011487
      Line 250, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest/run.log

            Offending '(gen_flops.gen_stable_chks.sig_unstable || (mubi_o == {NumCopies {$past(gen_flops.gen_stable_chks.mubi_in_sva_q, 2)}}))'
        UVM_ERROR @   5339221 ps: (prim_mubi4_sync.sv:120) [ASSERT FAILED] OutputDelay_A
        UVM_INFO @   5339221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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