CLKMGR Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.160s	111.274us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	72.962us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	12.480s	2.556ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.200s	231.504us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.790s	54.345us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
		clkmgr_csr_aliasing	2.200s	231.504us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.310s	203.275us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.140s	391.733us	50	50	100.00
V2	extclk	clkmgr_extclk	1.270s	179.038us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.040s	166.702us	50	50	100.00
V2	jitter	clkmgr_smoke	1.160s	111.274us	50	50	100.00
V2	frequency	clkmgr_frequency	17.670s	2.361ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.130s	2.297ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.670s	2.361ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	2.070m	16.678ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.950s	120.280us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.430s	219.657us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.640s	1.448ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.640s	1.448ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	72.962us	5	5	100.00
		clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
		clkmgr_csr_aliasing	2.200s	231.504us	5	5	100.00
		clkmgr_same_csr_outstanding	2.020s	279.671us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	72.962us	5	5	100.00
		clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
		clkmgr_csr_aliasing	2.200s	231.504us	5	5	100.00
		clkmgr_same_csr_outstanding	2.020s	279.671us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.380s	316.375us	5	5	100.00
		clkmgr_tl_intg_err	3.600s	447.070us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.750s	351.490us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.750s	351.490us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.750s	351.490us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.750s	351.490us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.910s	533.671us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.600s	447.070us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.670s	2.361ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.130s	2.297ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.750s	351.490us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.740s	329.961us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.180s	99.338us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.250s	144.554us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.250s	148.315us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.570s	250.367us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.380s	316.375us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.970s	113.892us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.380s	316.375us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.810s	1.146ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	33.958m	472.244ms	14	50	28.00
V3		TOTAL			64	100	64.00
		TOTAL			974	1010	96.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 20 failures:
  • Test clkmgr_stress_all_with_rand_reset has 20 failures.

    • 1.clkmgr_stress_all_with_rand_reset.7567330273208297040032603731462668434968561312158699952880771646557740802035
      Line 426, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6868638890 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 6868638890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.clkmgr_stress_all_with_rand_reset.47075444145350386882826303334327805242447370295151598474848877995234906007790
      Line 858, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68903765548 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 68903765548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 16 failures:
  • Test clkmgr_stress_all_with_rand_reset has 16 failures.

    • 0.clkmgr_stress_all_with_rand_reset.14356109163746915713361302025211438667496285986415102548343220271516793136928
      Line 621, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11656476919 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 11656476919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_stress_all_with_rand_reset.5900179336343349128904698790242728350863763245107782881293291312800646501105
      Line 801, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15688266543 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 15688266543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

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