CLKMGR Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.740s	309.685us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.320s	218.681us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	13.100s	2.565ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.720s	62.683us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.050s	120.318us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	62.683us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.900s	50.113us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.250s	141.017us	50	50	100.00
V2	extclk	clkmgr_extclk	1.580s	258.082us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.820s	39.852us	50	50	100.00
V2	jitter	clkmgr_smoke	1.740s	309.685us	50	50	100.00
V2	frequency	clkmgr_frequency	19.400s	2.477ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	14.410s	2.061ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.400s	2.477ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.129m	8.368ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.840s	88.339us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.360s	224.418us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.390s	703.643us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.390s	703.643us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.320s	218.681us	5	5	100.00
		clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	62.683us	5	5	100.00
		clkmgr_same_csr_outstanding	3.000s	797.739us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.320s	218.681us	5	5	100.00
		clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
		clkmgr_csr_aliasing	1.720s	62.683us	5	5	100.00
		clkmgr_same_csr_outstanding	3.000s	797.739us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.600s	578.307us	5	5	100.00
		clkmgr_tl_intg_err	3.400s	436.845us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	4.750s	1.366ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	4.750s	1.366ms	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	4.750s	1.366ms	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	4.750s	1.366ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.810s	491.871us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.400s	436.845us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.400s	2.477ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	14.410s	2.061ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	4.750s	1.366ms	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.880s	342.679us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.970s	375.358us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.980s	386.323us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.680s	285.432us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.690s	307.474us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.600s	578.307us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.010s	116.446us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.600s	578.307us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.800s	2.399ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	37.271m	515.716ms	18	50	36.00
V3		TOTAL			68	100	68.00
		TOTAL			978	1010	96.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.76	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 18 failures:
  • Test clkmgr_stress_all_with_rand_reset has 18 failures.

    • 1.clkmgr_stress_all_with_rand_reset.83494075964593509807378927898058980316317952500902380477505727644256932291055
      Line 576, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12648279092 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 12648279092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_stress_all_with_rand_reset.61222409202118697290883844442072481433575001657893643700768117838859286908483
      Line 268, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 610784638 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 610784638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 14 failures:
  • Test clkmgr_stress_all_with_rand_reset has 14 failures.

    • 6.clkmgr_stress_all_with_rand_reset.70773736386359997478210282216486869600242245259708188693548958083597839633749
      Line 1373, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31926411153 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 31926411153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.clkmgr_stress_all_with_rand_reset.91711622036579820856798471220957911661946839263422733857752519373718485005089
      Line 904, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14592877000 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 14592877000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

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