CLKMGR Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.700s	290.697us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.010s	93.364us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	16.870s	4.085ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.190s	342.717us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.940s	34.623us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
		clkmgr_csr_aliasing	2.190s	342.717us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.070s	135.289us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.870s	294.015us	50	50	100.00
V2	extclk	clkmgr_extclk	1.360s	188.815us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.070s	147.731us	50	50	100.00
V2	jitter	clkmgr_smoke	1.700s	290.697us	50	50	100.00
V2	frequency	clkmgr_frequency	18.100s	2.362ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.460s	2.301ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.100s	2.362ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.364m	11.170ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.900s	113.643us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.090s	92.243us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.090s	532.310us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.090s	532.310us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.010s	93.364us	5	5	100.00
		clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
		clkmgr_csr_aliasing	2.190s	342.717us	5	5	100.00
		clkmgr_same_csr_outstanding	2.040s	306.135us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.010s	93.364us	5	5	100.00
		clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
		clkmgr_csr_aliasing	2.190s	342.717us	5	5	100.00
		clkmgr_same_csr_outstanding	2.040s	306.135us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.340s	569.608us	5	5	100.00
		clkmgr_tl_intg_err	3.640s	609.478us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.710s	428.031us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.710s	428.031us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.710s	428.031us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.710s	428.031us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.110s	998.221us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.640s	609.478us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.100s	2.362ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.460s	2.301ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.710s	428.031us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.020s	419.058us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.230s	188.275us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.500s	252.972us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.180s	100.618us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.270s	188.232us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.340s	569.608us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.160s	156.278us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.340s	569.608us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	6.710s	1.239ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.634m	362.336ms	19	50	38.00
V3		TOTAL			69	100	69.00
		TOTAL			979	1010	96.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (clkmgr_frequency_vseq.sv:204) virtual_sequencer [clkmgr_frequency_vseq] Unexpected recoverable timeout error *b* has 19 failures:
  • Test clkmgr_stress_all_with_rand_reset has 19 failures.

    • 6.clkmgr_stress_all_with_rand_reset.105811257655562955872173930933872378810309389203515053205701574670856955521118
      Line 275, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1480894010 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 1480894010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.clkmgr_stress_all_with_rand_reset.94222160980720683284367404713913237228029697410572056711376561741508599037190
      Line 1251, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40724385950 ps: (clkmgr_frequency_vseq.sv:204) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Unexpected recoverable timeout error 0b11111
        UVM_INFO @ 40724385950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:368) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* has 12 failures:
  • Test clkmgr_stress_all_with_rand_reset has 12 failures.

    • 0.clkmgr_stress_all_with_rand_reset.66090666945558517748251167212604426076844989130646736578360235403775122010270
      Line 747, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13375815007 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 13375815007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_stress_all_with_rand_reset.53991048240672061322163081628388072907594344331710566605473148816414061454368
      Line 335, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 366143345 ps: (clkmgr_base_vseq.sv:368) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for measurement recoverable error, expected 0b00000, got 0b11111
        UVM_INFO @ 366143345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

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