CLKMGR Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.450s	223.748us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.380s	242.804us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.560s	763.170us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.120s	219.612us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.020s	38.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
		clkmgr_csr_aliasing	2.120s	219.612us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.180s	172.242us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.790s	295.569us	50	50	100.00
V2	extclk	clkmgr_extclk	1.230s	149.600us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.160s	199.599us	50	50	100.00
V2	jitter	clkmgr_smoke	1.450s	223.748us	50	50	100.00
V2	frequency	clkmgr_frequency	16.810s	2.122ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.080s	2.300ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.810s	2.122ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.008m	8.372ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.020s	136.905us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.370s	204.614us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.270s	1.430ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.270s	1.430ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.380s	242.804us	5	5	100.00
		clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
		clkmgr_csr_aliasing	2.120s	219.612us	5	5	100.00
		clkmgr_same_csr_outstanding	1.980s	338.589us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.380s	242.804us	5	5	100.00
		clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
		clkmgr_csr_aliasing	2.120s	219.612us	5	5	100.00
		clkmgr_same_csr_outstanding	1.980s	338.589us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	9.210s	2.416ms	5	5	100.00
		clkmgr_tl_intg_err	4.070s	686.570us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.070s	543.140us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.070s	543.140us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.070s	543.140us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.070s	543.140us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.570s	1.127ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.070s	686.570us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.810s	2.122ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.080s	2.300ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.070s	543.140us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.670s	276.205us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.890s	359.981us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.400s	187.661us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.730s	302.517us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.460s	200.725us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	9.210s	2.416ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.980s	62.755us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	9.210s	2.416ms	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.440s	1.332ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.529m	210.234ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1008	1010	99.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:755) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
  • Test clkmgr_stress_all_with_rand_reset has 2 failures.

    • 34.clkmgr_stress_all_with_rand_reset.1361404788682727609037282766129103469503996921400230548915774795457645992560
      Line 483, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19053119579 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 19053119579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.clkmgr_stress_all_with_rand_reset.58402289799445898054076746913261062762903345557561898661885023528179513582286
      Line 475, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35035023166 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 35035023166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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