CLKMGR Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.250s 157.602us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.910s 52.908us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 15.410s 2.803ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.750s 389.936us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.950s 409.666us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
clkmgr_csr_aliasing 2.750s 389.936us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.350s 218.791us 50 50 100.00
V2 trans_enables clkmgr_trans 1.440s 245.632us 50 50 100.00
V2 extclk clkmgr_extclk 1.890s 377.289us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.160s 195.547us 50 50 100.00
V2 jitter clkmgr_smoke 1.250s 157.602us 50 50 100.00
V2 frequency clkmgr_frequency 16.610s 2.121ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.310s 2.420ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 16.610s 2.121ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.538m 12.698ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 60.393us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.450s 260.164us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 7.450s 1.856ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 7.450s 1.856ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.910s 52.908us 5 5 100.00
clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
clkmgr_csr_aliasing 2.750s 389.936us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 213.903us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.910s 52.908us 5 5 100.00
clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
clkmgr_csr_aliasing 2.750s 389.936us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 213.903us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 8.130s 1.968ms 5 5 100.00
clkmgr_tl_intg_err 4.000s 561.575us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.210s 585.812us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.210s 585.812us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.210s 585.812us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.210s 585.812us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.790s 323.457us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.000s 561.575us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 16.610s 2.121ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.310s 2.420ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.210s 585.812us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.640s 235.354us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.270s 158.360us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.520s 248.127us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.640s 253.939us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.780s 330.780us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 8.130s 1.968ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.170s 161.098us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 8.130s 1.968ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.170s 1.319ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 39.157m 676.690ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results