CLKMGR Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.530s 246.421us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.930s 98.038us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.900s 1.905ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.940s 218.983us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.950s 342.879us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
clkmgr_csr_aliasing 1.940s 218.983us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.250s 167.218us 50 50 100.00
V2 trans_enables clkmgr_trans 1.900s 356.558us 50 50 100.00
V2 extclk clkmgr_extclk 1.880s 364.746us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.020s 112.142us 50 50 100.00
V2 jitter clkmgr_smoke 1.530s 246.421us 50 50 100.00
V2 frequency clkmgr_frequency 18.730s 2.479ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.060s 2.421ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.730s 2.479ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.574m 13.385ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.850s 86.914us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.460s 247.149us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.220s 1.561ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.220s 1.561ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.930s 98.038us 5 5 100.00
clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
clkmgr_csr_aliasing 1.940s 218.983us 5 5 100.00
clkmgr_same_csr_outstanding 1.480s 89.455us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.930s 98.038us 5 5 100.00
clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
clkmgr_csr_aliasing 1.940s 218.983us 5 5 100.00
clkmgr_same_csr_outstanding 1.480s 89.455us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.890s 1.220ms 5 5 100.00
clkmgr_tl_intg_err 6.380s 1.395ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.100s 640.333us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.100s 640.333us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.100s 640.333us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.100s 640.333us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.630s 456.993us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 6.380s 1.395ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.730s 2.479ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.060s 2.421ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.100s 640.333us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.430s 167.134us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.460s 202.799us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.080s 105.686us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.720s 298.237us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.900s 392.766us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.890s 1.220ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.350s 244.518us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.890s 1.220ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.480s 1.336ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 29.466m 454.776ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results