CLKMGR Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.490s	200.895us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.910s	37.819us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	12.210s	1.915ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.420s	344.836us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.120s	320.692us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
		clkmgr_csr_aliasing	2.420s	344.836us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.010s	120.928us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.340s	146.181us	50	50	100.00
V2	extclk	clkmgr_extclk	1.490s	229.007us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.130s	162.513us	50	50	100.00
V2	jitter	clkmgr_smoke	1.490s	200.895us	50	50	100.00
V2	frequency	clkmgr_frequency	20.270s	2.480ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.740s	2.180ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	20.270s	2.480ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.256m	10.546ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.860s	101.168us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.540s	226.977us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.370s	1.109ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.370s	1.109ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.910s	37.819us	5	5	100.00
		clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
		clkmgr_csr_aliasing	2.420s	344.836us	5	5	100.00
		clkmgr_same_csr_outstanding	2.850s	660.760us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.910s	37.819us	5	5	100.00
		clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
		clkmgr_csr_aliasing	2.420s	344.836us	5	5	100.00
		clkmgr_same_csr_outstanding	2.850s	660.760us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	5.230s	950.221us	5	5	100.00
		clkmgr_tl_intg_err	3.960s	980.580us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.650s	337.347us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.650s	337.347us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.650s	337.347us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.650s	337.347us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.370s	385.406us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.960s	980.580us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	20.270s	2.480ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.740s	2.180ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.650s	337.347us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.620s	607.051us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.310s	154.110us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.350s	203.401us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.850s	336.151us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.280s	153.098us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.230s	950.221us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.980s	64.990us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.230s	950.221us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	9.420s	3.029ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	38.794m	541.707ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.47	99.11	95.68	100.00	100.00	98.71	97.02	98.80

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