CLKMGR Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.660s 287.776us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.910s 54.867us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.480s 1.751ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.030s 201.725us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.730s 627.178us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
clkmgr_csr_aliasing 2.030s 201.725us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.230s 170.511us 50 50 100.00
V2 trans_enables clkmgr_trans 2.030s 373.231us 50 50 100.00
V2 extclk clkmgr_extclk 1.760s 342.449us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.180s 202.873us 50 50 100.00
V2 jitter clkmgr_smoke 1.660s 287.776us 50 50 100.00
V2 frequency clkmgr_frequency 16.370s 2.123ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.610s 2.418ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 16.370s 2.123ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.329m 11.283ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.920s 126.430us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.110s 142.937us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.850s 701.503us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.850s 701.503us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.910s 54.867us 5 5 100.00
clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
clkmgr_csr_aliasing 2.030s 201.725us 5 5 100.00
clkmgr_same_csr_outstanding 2.910s 747.733us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.910s 54.867us 5 5 100.00
clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
clkmgr_csr_aliasing 2.030s 201.725us 5 5 100.00
clkmgr_same_csr_outstanding 2.910s 747.733us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.880s 1.435ms 5 5 100.00
clkmgr_tl_intg_err 3.930s 749.803us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.210s 743.693us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.210s 743.693us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.210s 743.693us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.210s 743.693us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.110s 711.251us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.930s 749.803us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 16.370s 2.123ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.610s 2.418ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.210s 743.693us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.060s 403.539us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.550s 264.507us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.550s 248.182us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.900s 375.593us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.750s 321.660us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.880s 1.435ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.960s 62.512us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.880s 1.435ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.940s 1.248ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 2.923m 41.536ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.49 99.15 95.80 100.00 100.00 98.81 97.02 98.63

Past Results