CLKMGR Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.450s 244.239us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.080s 147.119us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.090s 553.865us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.270s 266.066us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.920s 61.695us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
clkmgr_csr_aliasing 2.270s 266.066us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.010s 114.735us 50 50 100.00
V2 trans_enables clkmgr_trans 2.400s 471.311us 50 50 100.00
V2 extclk clkmgr_extclk 1.150s 103.227us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.030s 141.008us 50 50 100.00
V2 jitter clkmgr_smoke 1.450s 244.239us 50 50 100.00
V2 frequency clkmgr_frequency 17.260s 2.361ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.560s 2.055ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.260s 2.361ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.055m 11.929ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.810s 79.061us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.400s 225.624us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.010s 921.610us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.010s 921.610us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.080s 147.119us 5 5 100.00
clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
clkmgr_csr_aliasing 2.270s 266.066us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 207.212us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.080s 147.119us 5 5 100.00
clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
clkmgr_csr_aliasing 2.270s 266.066us 5 5 100.00
clkmgr_same_csr_outstanding 1.940s 207.212us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.000s 286.180us 5 5 100.00
clkmgr_tl_intg_err 5.900s 1.419ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.360s 736.567us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.360s 736.567us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.360s 736.567us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.360s 736.567us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.490s 439.460us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 5.900s 1.419ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.260s 2.361ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.560s 2.055ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.360s 736.567us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.830s 286.332us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.430s 247.899us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.480s 262.465us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.680s 288.841us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.170s 472.132us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.000s 286.180us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.960s 70.208us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.000s 286.180us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.840s 1.248ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 3.125m 44.049ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results